iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14	1	-1/+1
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
*	Do not the 'z' modifier in format string (another win32 fix)	Clifford Wolf	2014-10-11	1	-1/+1
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-0/+4
*	More idstring sort_by_* helpers and fixed tpl ordering in techmap	Clifford Wolf	2014-08-15	1	-4/+4
*	RIP $safe_pmux	Clifford Wolf	2014-08-14	1	-1/+1
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-27/+27
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-3/+3
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-2/+2
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	1	-8/+8
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-2/+6
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-28/+28
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-28/+28
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-4/+2
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-9/+9
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-9/+9
*	Some fixes to improve determinism	Clifford Wolf	2013-08-09	1	-4/+4
*	Improved method for finding fsm_expand candidates	Clifford Wolf	2013-03-25	1	-5/+7
*	Changed fsm_expand to merge multiplexers more aggressively	Clifford Wolf	2013-03-24	1	-1/+4
*	fixed typos	Johann Glaser	2013-03-18	1	-1/+1
*	Added help messages for fsm_* passes	Clifford Wolf	2013-03-01	1	-6/+19
*	initial import	Clifford Wolf	2013-01-05	1	-0/+255