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* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-1/+1
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* Do not the 'z' modifier in format string (another win32 fix)Clifford Wolf2014-10-111-1/+1
* namespace YosysClifford Wolf2014-09-271-0/+4
* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-151-4/+4
* RIP $safe_pmuxClifford Wolf2014-08-141-1/+1
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-27/+27
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-3/+3
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-2/+2
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-261-8/+8
* Manual fixes for new cell connections APIClifford Wolf2014-07-261-2/+6
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-28/+28
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-28/+28
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-4/+2
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-9/+9
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-9/+9
* Some fixes to improve determinismClifford Wolf2013-08-091-4/+4
* Improved method for finding fsm_expand candidatesClifford Wolf2013-03-251-5/+7
* Changed fsm_expand to merge multiplexers more aggressivelyClifford Wolf2013-03-241-1/+4
* fixed typosJohann Glaser2013-03-181-1/+1
* Added help messages for fsm_* passesClifford Wolf2013-03-011-6/+19
* initial importClifford Wolf2013-01-051-0/+255