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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-15 02:40:46 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-15 02:40:46 +0200 |
| commit | ca8711644975c128d45fd8e9434439c1266c00ac (patch) | |
| tree | d142e82fe2dbdebf77635a05862b383c81167e3b /passes/fsm/fsm_expand.cc | |
| parent | 8ff71b5ae506306d7981eb118874cd4f407b2bf8 (diff) | |
| download | yosys-ca8711644975c128d45fd8e9434439c1266c00ac.tar.gz yosys-ca8711644975c128d45fd8e9434439c1266c00ac.tar.bz2 yosys-ca8711644975c128d45fd8e9434439c1266c00ac.zip | |
More idstring sort_by_* helpers and fixed tpl ordering in techmap
Diffstat (limited to 'passes/fsm/fsm_expand.cc')
| -rw-r--r-- | passes/fsm/fsm_expand.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index 77821326d..d13643911 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -30,12 +30,12 @@ struct FsmExpand RTLIL::Module *module; RTLIL::Cell *fsm_cell; SigMap assign_map; - SigSet<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> sig2driver, sig2user; + SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> sig2driver, sig2user; CellTypes ct; - std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> merged_set; - std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> current_set; - std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> no_candidate_set; + std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> merged_set; + std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> current_set; + std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> no_candidate_set; bool already_optimized; int limit_transitions; |