iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
*	Added log_warning() API	Clifford Wolf	2014-11-09	1	-1/+1
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-0/+4
*	RIP $safe_pmux	Clifford Wolf	2014-08-14	1	-1/+1
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-1/+1
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-7/+7
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-2/+2
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	1	-1/+1
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-9/+9
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-9/+9
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-2/+2
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-2/+2
*	Fixes in fsm detect/extract for better detection of non-fsm circuits	Clifford Wolf	2013-12-06	1	-1/+1
*	Added detection for endless recursion in fsm_detect pass	Clifford Wolf	2013-10-30	1	-4/+15
*	fixed typos	Johann Glaser	2013-03-18	1	-3/+3
*	Added help messages for fsm_* passes	Clifford Wolf	2013-03-01	1	-2/+22
*	initial import	Clifford Wolf	2013-01-05	1	-0/+160