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* Squelch trailing whitespaceLarry Doolittle2017-04-121-2/+2
* Further improved fsm_detect output, attempt to detect self-resetting circuitsClifford Wolf2016-07-091-6/+68
* Added printing of some warning messages to fsm_detectClifford Wolf2016-07-091-14/+61
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Do not detect fsm state registers with init attributeClifford Wolf2015-09-211-0/+2
* Added $logic_not handling to fsm_detectClifford Wolf2015-09-181-0/+2
* Bugfix in fsm_detect for complex muxtreesClifford Wolf2015-08-181-15/+23
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* Added log_warning() APIClifford Wolf2014-11-091-1/+1
* namespace YosysClifford Wolf2014-09-271-0/+4
* RIP $safe_pmuxClifford Wolf2014-08-141-1/+1
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-1/+1
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-7/+7
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-2/+2
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-261-1/+1
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-9/+9
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-9/+9
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-2/+2
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-2/+2
* Fixes in fsm detect/extract for better detection of non-fsm circuitsClifford Wolf2013-12-061-1/+1
* Added detection for endless recursion in fsm_detect passClifford Wolf2013-10-301-4/+15
* fixed typosJohann Glaser2013-03-181-3/+3
* Added help messages for fsm_* passesClifford Wolf2013-03-011-2/+22
* initial importClifford Wolf2013-01-051-0/+160