| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Clean up `passes/cmds/splice.cc`. | Alberto Gonzalez | 2020-04-06 | 1 | -18/+14 |
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| * | kernel: big fat patch to use more ID::*, otherwise ID(*) | Eddie Hung | 2020-04-02 | 1 | -7/+7 |
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| * | kernel: use more ID::* | Eddie Hung | 2020-04-02 | 1 | -7/+7 |
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| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
| | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | ||||
| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
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| * | renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit() | Clifford Wolf | 2015-10-24 | 1 | -1/+1 |
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| * | Spell check (by Larry Doolittle) | Clifford Wolf | 2015-08-14 | 1 | -1/+1 |
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| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -3/+3 |
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| * | Added "splice -wires" | Clifford Wolf | 2015-04-13 | 1 | -9/+20 |
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| * | Fixed memory corruption in "splice" command | Clifford Wolf | 2014-12-29 | 1 | -13/+16 |
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| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -0/+4 |
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| * | Corrected spelling mistakes found by lintian | Ruben Undheim | 2014-09-06 | 1 | -2/+2 |
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| * | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 1 | -4/+4 |
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| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -7/+7 |
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| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
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| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -2/+2 |
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| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -3/+3 |
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| * | Changed more code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 1 | -5/+5 |
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| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -1/+1 |
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| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -10/+10 |
| | | | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' | ||||
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -10/+10 |
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| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -8/+2 |
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| * | Removed RTLIL::SigSpec::optimize() | Clifford Wolf | 2014-07-23 | 1 | -2/+0 |
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| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -9/+9 |
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| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -9/+9 |
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| * | Removed deprecated module->new_wire() | Clifford Wolf | 2014-07-21 | 1 | -2/+2 |
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| * | Added various new options to splice command | Clifford Wolf | 2014-02-08 | 1 | -5/+105 |
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| * | Now also move net labes to the right position in splice cmd | Clifford Wolf | 2014-02-08 | 1 | -3/+10 |
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| * | Added splice command | Clifford Wolf | 2014-02-07 | 1 | -0/+252 |
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index : iCE40/yosys | |
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