aboutsummaryrefslogtreecommitdiffstats
path: root/passes/cmds/splice.cc
Commit message (Expand)AuthorAgeFilesLines
* Clean up `passes/cmds/splice.cc`.Alberto Gonzalez2020-04-061-18/+14
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-7/+7
* kernel: use more ID::*Eddie Hung2020-04-021-7/+7
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()Clifford Wolf2015-10-241-1/+1
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-1/+1
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* Added "splice -wires"Clifford Wolf2015-04-131-9/+20
* Fixed memory corruption in "splice" commandClifford Wolf2014-12-291-13/+16
* namespace YosysClifford Wolf2014-09-271-0/+4
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-061-2/+2
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-4/+4
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-7/+7
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-2/+2
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-3/+3
* Changed more code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-5/+5
* Manual fixes for new cell connections APIClifford Wolf2014-07-261-1/+1
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-10/+10
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-10/+10
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-8/+2
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-231-2/+0
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-9/+9
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-9/+9
* Removed deprecated module->new_wire()Clifford Wolf2014-07-211-2/+2
* Added various new options to splice commandClifford Wolf2014-02-081-5/+105
* Now also move net labes to the right position in splice cmdClifford Wolf2014-02-081-3/+10
* Added splice commandClifford Wolf2014-02-071-0/+252