| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
| * | renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit() | Clifford Wolf | 2015-10-24 | 1 | -1/+1 |
| * | Spell check (by Larry Doolittle) | Clifford Wolf | 2015-08-14 | 1 | -1/+1 |
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -3/+3 |
| * | Added "splice -wires" | Clifford Wolf | 2015-04-13 | 1 | -9/+20 |
| * | Fixed memory corruption in "splice" command | Clifford Wolf | 2014-12-29 | 1 | -13/+16 |
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -0/+4 |
| * | Corrected spelling mistakes found by lintian | Ruben Undheim | 2014-09-06 | 1 | -2/+2 |
| * | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 1 | -4/+4 |
| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -7/+7 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -2/+2 |
| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -3/+3 |
| * | Changed more code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 1 | -5/+5 |
| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -1/+1 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -10/+10 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -10/+10 |
| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -8/+2 |
| * | Removed RTLIL::SigSpec::optimize() | Clifford Wolf | 2014-07-23 | 1 | -2/+0 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -9/+9 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -9/+9 |
| * | Removed deprecated module->new_wire() | Clifford Wolf | 2014-07-21 | 1 | -2/+2 |
| * | Added various new options to splice command | Clifford Wolf | 2014-02-08 | 1 | -5/+105 |
| * | Now also move net labes to the right position in splice cmd | Clifford Wolf | 2014-02-08 | 1 | -3/+10 |
| * | Added splice command | Clifford Wolf | 2014-02-07 | 1 | -0/+252 |
