iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Added "Nx" syntax to "show" command for repeating SigChunks	Clifford Wolf	2014-11-08	1	-6/+8
*	Header changes so it will compile on VS	William Speirs	2014-10-17	1	-1/+4
*	Added run_command() api to replace system() and popen()	Clifford Wolf	2014-10-12	1	-3/+3
*	Added format __attribute__ to stringf()	Clifford Wolf	2014-10-10	1	-1/+1
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-1/+1
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-0/+4
*	Alphabetically sort port names in "show" output	Clifford Wolf	2014-09-19	1	-0/+3
*	Removed references to yosys-svgviewer from docs	Clifford Wolf	2014-09-02	1	-2/+2
*	Using "xdot" instead of "yosys-svgviewer" in show command	Clifford Wolf	2014-09-02	1	-4/+3
*	Changed frontend-api from FILE to std::istream	Clifford Wolf	2014-08-23	1	-4/+4
*	Added emscripten (emcc) support to build system and some build fixes	Clifford Wolf	2014-08-22	1	-1/+8
*	Added "show -signed"	Clifford Wolf	2014-08-04	1	-5/+17
*	Fixes in show command (related to new IdString)	Clifford Wolf	2014-08-03	1	-20/+18
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	1	-1/+1
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-11/+13
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-1/+1
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-2/+2
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-3/+3
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-1/+1
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-3/+3
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-5/+5
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-5/+5
*	Various RTLIL::SigSpec related code cleanups	Clifford Wolf	2014-07-25	1	-3/+3
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-2/+2
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-3/+0
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22	1	-2/+2
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-17/+17
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-17/+17
*	Improved seeding of color rng in show command	Clifford Wolf	2014-07-18	1	-1/+3
*	fixed syntax error in dot file created by "show" command	Clifford Wolf	2014-05-10	1	-1/+1
*	- kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_shar...	Siesh1oo	2014-03-12	1	-1/+2
*	Added show -notitle option	Clifford Wolf	2014-02-02	1	-4/+14
*	Added show -color support for cells and finished show -label implementation	Clifford Wolf	2014-02-01	1	-13/+36
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	1	-1/+1
*	Fixes and improvements in "show" command	Clifford Wolf	2013-11-28	1	-10/+42
*	Added "src" attribute to processes	Clifford Wolf	2013-11-28	1	-1/+4
*	Added support for "show -pause" and "show -format dot"	Clifford Wolf	2013-11-28	1	-6/+30
*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22	1	-3/+3
*	Added placeholder check to dfflibmap and cleaned up some other placeholder ch...	Clifford Wolf	2013-10-31	1	-2/+2
*	Fixed handling of boolean attributes (passes)	Clifford Wolf	2013-10-24	1	-2/+2
*	Some minor documentation fixes	Clifford Wolf	2013-08-21	1	-1/+1
*	Renamed yosys-show temp files to be dot-files in the users home directory	Clifford Wolf	2013-06-12	1	-3/+3
*	Look for yosys-abc and yosys-svgviewer where the main exe is	Clifford Wolf	2013-06-09	1	-1/+1
*	Moved cmds from kernel/ to passes/cmds/	Clifford Wolf	2013-06-08	1	-0/+684