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author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 10:18:00 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 11:18:30 +0200 |
commit | 10e5791c5e5660cb784503d36439ee90d61eb06b (patch) | |
tree | d7bd3d8f1d0254e14fcf68ce25545f42afab9724 /passes/cmds/show.cc | |
parent | d088854b47f5f77c6a62be2ba4b895164938d7a2 (diff) | |
download | yosys-10e5791c5e5660cb784503d36439ee90d61eb06b.tar.gz yosys-10e5791c5e5660cb784503d36439ee90d61eb06b.tar.bz2 yosys-10e5791c5e5660cb784503d36439ee90d61eb06b.zip |
Refactoring: Renamed RTLIL::Design::modules to modules_
Diffstat (limited to 'passes/cmds/show.cc')
-rw-r--r-- | passes/cmds/show.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 18af8dfce..7ab1daf00 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -506,7 +506,7 @@ struct ShowWorker design->optimize(); page_counter = 0; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { module = mod_it.second; if (!design->selected_module(module->name)) @@ -692,7 +692,7 @@ struct ShowPass : public Pass { if (format != "ps") { int modcount = 0; - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (mod_it.second->get_bool_attribute("\\blackbox")) continue; if (mod_it.second->cells_.empty() && mod_it.second->connections().empty()) |