| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | substr() -> compare() | Eddie Hung | 2019-08-07 | 1 | -1/+1 |
| * | Add "wbflip" command | Clifford Wolf | 2019-04-20 | 1 | -0/+39 |
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -6/+6 |
| * | Added "setparam -type" | Clifford Wolf | 2016-10-19 | 1 | -3/+13 |
| * | Support for abstract modules in chparam | Clifford Wolf | 2016-03-21 | 1 | -0/+6 |
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -5/+5 |
| * | Bugfix in chparam | Clifford Wolf | 2015-06-30 | 1 | -6/+5 |
| * | Added support for "file names with blanks" | Clifford Wolf | 2015-04-08 | 1 | -20/+14 |
| * | Added "chparam -list" | Clifford Wolf | 2015-04-07 | 1 | -0/+21 |
| * | typo fix | Clifford Wolf | 2015-04-07 | 1 | -1/+1 |
| * | Added "chparam" command | Clifford Wolf | 2015-04-07 | 1 | -0/+57 |
| * | Added Yosys::{dict,nodict,vector} container types | Clifford Wolf | 2014-12-26 | 1 | -1/+1 |
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -0/+4 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -2/+2 |
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -2/+2 |
| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Added setattr and setparam commands | Clifford Wolf | 2014-02-05 | 1 | -0/+180 |
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index : iCE40/yosys | |
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