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author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:49:51 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:49:51 +0200 |
commit | f9946232adf887e5aa4a48c64f88eaa17e424009 (patch) | |
tree | 39594b3287c3369752668456c4a6b1735fb66e77 /passes/cmds/setattr.cc | |
parent | d7916a49aff3c47b7c1ce07abe3b6e3d5714079b (diff) | |
download | yosys-f9946232adf887e5aa4a48c64f88eaa17e424009.tar.gz yosys-f9946232adf887e5aa4a48c64f88eaa17e424009.tar.bz2 yosys-f9946232adf887e5aa4a48c64f88eaa17e424009.zip |
Refactoring: Renamed RTLIL::Module::wires to wires_
Diffstat (limited to 'passes/cmds/setattr.cc')
-rw-r--r-- | passes/cmds/setattr.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc index 8d98df719..0b4f2a8a2 100644 --- a/passes/cmds/setattr.cc +++ b/passes/cmds/setattr.cc @@ -111,7 +111,7 @@ struct SetattrPass : public Pass { if (!design->selected(module)) continue; - for (auto &it : module->wires) + for (auto &it : module->wires_) if (design->selected(module, it.second)) do_setunset(it.second->attributes, setunset_list); |