iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	rtlil: Make Process handling more uniform with Cell and Wire.	Marcelina Kościelnicka	2021-07-12	1	-6/+4
*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	1	-1/+1
*	kernel/rtlil: Extract some helpers for checking memory cell types.	Marcelina Kościelnicka	2021-05-22	1	-1/+1
*	Use C++11 final/override keywords.	whitequark	2020-06-18	1	-2/+2
*	Clean up `passes/cmds/delete.cc`.	Alberto Gonzalez	2020-04-06	1	-24/+19
*	kernel: big fat patch to use more ID::, otherwise ID()	Eddie Hung	2020-04-02	1	-2/+2
*	More use of IdString::in()	Eddie Hung	2019-08-15	1	-1/+1
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
*	Renamed hashmap.h to hashlib.h, some related improvements	Clifford Wolf	2014-12-28	1	-2/+2
*	More hashtable finetuning	Clifford Wolf	2014-12-27	1	-2/+2
*	Replaced std::unordered_set (nodict) with Yosys::pool	Clifford Wolf	2014-12-26	1	-4/+4
*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26	1	-4/+4
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-3/+5
*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02	1	-3/+3
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-3/+3
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-2/+2
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-30/+5
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-5/+4
*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23	1	-2/+3
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22	1	-1/+1
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-1/+1
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-1/+1
*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21	1	-1/+1
*	Added delete {-input\|-output\|-port}	Clifford Wolf	2014-02-09	1	-5/+36
*	Bugfix in delete command	Clifford Wolf	2014-02-09	1	-1/+3
*	Added delete command	Clifford Wolf	2014-02-02	1	-0/+134