| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Less verbose ABC output | Clifford Wolf | 2014-12-29 | 1 | -1/+2 |
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -3/+4 |
| * | Renamed $lut ports to follow A-Y naming scheme | Clifford Wolf | 2014-08-15 | 1 | -2/+2 |
| * | Added module->ports | Clifford Wolf | 2014-08-14 | 1 | -2/+1 |
| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -5/+5 |
| * | Added module->design and cell->module, wire->module pointers | Clifford Wolf | 2014-07-31 | 1 | -1/+1 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -8/+8 |
| * | Changed a lot of code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 1 | -16/+6 |
| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -1/+1 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -6/+6 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -6/+6 |
| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -18/+6 |
| * | Removed RTLIL::SigSpec::optimize() | Clifford Wolf | 2014-07-23 | 1 | -3/+0 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -5/+5 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -5/+5 |
| * | Fixed memory corruption in passes/abc/blifparse.cc | Clifford Wolf | 2014-03-11 | 1 | -1/+1 |
| * | Fixed use of limited length buffer in ABC blif parser | Clifford Wolf | 2013-12-31 | 1 | -7/+16 |
| * | Added abc -dff and -clk support | Clifford Wolf | 2013-12-31 | 1 | -1/+27 |
| * | Always use BLIF as ABC output format | Clifford Wolf | 2013-12-31 | 1 | -0/+26 |
| * | Renamed temp module generated by "abc" pass from "logic" to "netlist" | Clifford Wolf | 2013-11-19 | 1 | -1/+1 |
| * | Fixed abc pass blif parser for constant bits | Clifford Wolf | 2013-11-13 | 1 | -18/+57 |
| * | Added $lut cells and abc lut mapping support | Clifford Wolf | 2013-07-23 | 1 | -0/+168 |
