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author | Clifford Wolf <clifford@clifford.at> | 2014-07-25 15:05:18 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-25 17:56:19 +0200 |
commit | 2bec47a4045d23d46e7d300cbf80b2dce1a549a9 (patch) | |
tree | 991a75afe9b009486a57834fefee075ec695a28c /passes/abc/blifparse.cc | |
parent | 5826670009e1018734de49aaf1554cb8a43d09d7 (diff) | |
download | yosys-2bec47a4045d23d46e7d300cbf80b2dce1a549a9.tar.gz yosys-2bec47a4045d23d46e7d300cbf80b2dce1a549a9.tar.bz2 yosys-2bec47a4045d23d46e7d300cbf80b2dce1a549a9.zip |
Use only module->addCell() and module->remove() to create and delete cells
Diffstat (limited to 'passes/abc/blifparse.cc')
-rw-r--r-- | passes/abc/blifparse.cc | 24 |
1 files changed, 6 insertions, 18 deletions
diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index 04977b369..e7feb1877 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -127,36 +127,27 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) module->add(wire); } - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - cell->type = dff_name; + RTLIL::Cell *cell = module->addCell(NEW_ID, dff_name); cell->connections["\\D"] = module->wires.at(RTLIL::escape_id(d)); cell->connections["\\Q"] = module->wires.at(RTLIL::escape_id(q)); - module->add(cell); continue; } if (!strcmp(cmd, ".gate")) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - module->add(cell); - char *p = strtok(NULL, " \t\r\n"); if (p == NULL) goto error; - cell->type = RTLIL::escape_id(p); + + RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(p)); while ((p = strtok(NULL, " \t\r\n")) != NULL) { char *q = strchr(p, '='); if (q == NULL || !q[0] || !q[1]) goto error; *(q++) = 0; - if (module->wires.count(RTLIL::escape_id(q)) == 0) { - RTLIL::Wire *wire = new RTLIL::Wire; - wire->name = RTLIL::escape_id(q); - module->add(wire); - } + if (module->wires.count(RTLIL::escape_id(q)) == 0) + module->addWire(RTLIL::escape_id(q)); cell->connections[RTLIL::escape_id(p)] = module->wires.at(RTLIL::escape_id(q)); } continue; @@ -212,16 +203,13 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) goto continue_without_read; } - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - cell->type = "$lut"; + RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut"); cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size()); cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size()); cell->connections["\\I"] = input_sig; cell->connections["\\O"] = output_sig; lutptr = &cell->parameters.at("\\LUT"); lut_default_state = RTLIL::State::Sx; - module->add(cell); continue; } |