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Author
Age
Files
Lines
*
Fixed creation of command reference in manual
Clifford Wolf
2015-02-09
1
-5
/
+5
*
Updated command reference in manual
Clifford Wolf
2015-02-09
1
-75
/
+440
*
Various presentation fixes
Clifford Wolf
2015-02-09
2
-8
/
+15
*
Added $equiv cell type
Clifford Wolf
2015-01-19
1
-1
/
+1
*
Improvements in CodingReadme
Clifford Wolf
2014-12-31
1
-8
/
+13
*
Added more documentation fixmes for nontrivial register cells
Clifford Wolf
2014-12-08
1
-1
/
+9
*
manual/presentation.tex: bg option is unknown with beamer 3.3 in beamercolorbox
Fabien Marteau
2014-12-07
1
-1
/
+1
*
suppressing semi-colon at the end of dot files
Fabien Marteau
2014-12-05
19
-19
/
+19
*
Added some missing .gitignore in manual/
Clifford Wolf
2014-12-04
2
-0
/
+4
*
Some fixes in stubnets example
Clifford Wolf
2014-11-24
1
-3
/
+5
*
Some fixes in presentation
Clifford Wolf
2014-11-08
2
-2
/
+2
*
Various documentation updates
Clifford Wolf
2014-11-08
12
-108
/
+1276
*
Renamed SIZE() to GetSize() because of name collision on Win32
Clifford Wolf
2014-10-10
2
-3
/
+3
*
Added $lcu cell type
Clifford Wolf
2014-09-08
1
-1
/
+1
*
Corrected spelling mistakes found by lintian
Ruben Undheim
2014-09-06
5
-13
/
+13
*
Removed $bu0 cell type
Clifford Wolf
2014-09-04
3
-8
/
+2
*
Removed references to yosys-svgviewer from docs
Clifford Wolf
2014-09-02
2
-21
/
+10
*
Added $alu cell type
Clifford Wolf
2014-08-30
1
-0
/
+4
*
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...
Clifford Wolf
2014-08-16
1
-0
/
+4
*
Renamed $_INV_ cell type to $_NOT_
Clifford Wolf
2014-08-15
4
-6
/
+6
*
Removed old doc references to $safe_pmux
Clifford Wolf
2014-08-15
2
-5
/
+1
*
RIP $safe_pmux
Clifford Wolf
2014-08-14
1
-1
/
+1
*
Replaced sha1 implementation
Clifford Wolf
2014-08-01
2
-9
/
+3
*
Added module->design and cell->module, wire->module pointers
Clifford Wolf
2014-07-31
2
-24
/
+17
*
Renamed "stdcells.v" to "techmap.v"
Clifford Wolf
2014-07-31
1
-1
/
+1
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
2
-5
/
+5
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
2
-2
/
+2
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
2
-4
/
+4
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
1
-1
/
+1
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
1
-1
/
+1
*
Fixed manual/CHAPTER_Prog/stubnets.cc
Clifford Wolf
2014-07-23
1
-2
/
+2
*
Removed RTLIL::SigSpec::expand() method
Clifford Wolf
2014-07-23
1
-12
/
+7
*
Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal
Clifford Wolf
2014-07-16
1
-3
/
+4
*
small changes in presentation
Clifford Wolf
2014-07-02
1
-5
/
+2
*
Tiny fix in presentation
Clifford Wolf
2014-06-29
1
-1
/
+1
*
Progress in presentation
Clifford Wolf
2014-06-29
2
-0
/
+97
*
Progress in presentation
Clifford Wolf
2014-06-26
7
-79
/
+105
*
Progress in presentation
Clifford Wolf
2014-06-22
7
-42
/
+503
*
fixed typo
Clifford Wolf
2014-06-21
1
-1
/
+1
*
Progress in presentation
Clifford Wolf
2014-06-21
9
-23
/
+188
*
Progress in presentation
Clifford Wolf
2014-06-14
5
-3
/
+109
*
Progress in presentation
Clifford Wolf
2014-05-06
1
-8
/
+63
*
Typos and grammar fixes through chapter 4.
Anthony J. Bentley
2014-05-02
2
-32
/
+32
*
Typos and grammar fixes through chapter 2.
Anthony J. Bentley
2014-04-11
3
-21
/
+21
*
POSIX find requires a path argument.
Anthony J. Bentley
2014-04-04
1
-1
/
+1
*
Progress in presentation
Clifford Wolf
2014-02-21
6
-32
/
+113
*
Progress in presentation
Clifford Wolf
2014-02-21
5
-19
/
+177
*
Progress in presentation
Clifford Wolf
2014-02-20
4
-11
/
+51
*
Progress in presentation
Clifford Wolf
2014-02-20
5
-0
/
+207
*
Progress in presentation
Clifford Wolf
2014-02-20
10
-10
/
+152
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