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authorClifford Wolf <clifford@clifford.at>2014-10-10 16:59:44 +0200
committerClifford Wolf <clifford@clifford.at>2014-10-10 17:07:24 +0200
commit4569a747f8af3880e23408eb93323afc8088b78b (patch)
tree81dcea51020173cd4951e8649f8bd8305e7c2591 /manual
parentc7f5aab625bb90e766c1852592fdf42c951716c0 (diff)
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Renamed SIZE() to GetSize() because of name collision on Win32
Diffstat (limited to 'manual')
-rw-r--r--manual/CHAPTER_Prog/stubnets.cc4
-rw-r--r--manual/PRESENTATION_Prog/my_cmd.cc2
2 files changed, 3 insertions, 3 deletions
diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc
index ef4b1245d..8880af5a6 100644
--- a/manual/CHAPTER_Prog/stubnets.cc
+++ b/manual/CHAPTER_Prog/stubnets.cc
@@ -62,7 +62,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
// for each bit (unless it is a constant):
// check if it is used at least two times and add to stub_bits otherwise
- for (int i = 0; i < SIZE(sig); i++)
+ for (int i = 0; i < GetSize(sig); i++)
if (sig[i].wire != NULL && (bit_usage_count[sig[i]] + usage_offset) < 2)
stub_bits.insert(i);
@@ -72,7 +72,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
// report stub bits and/or stub wires, don't report single bits
// if called with report_bits set to false.
- if (SIZE(stub_bits) == SIZE(sig)) {
+ if (GetSize(stub_bits) == GetSize(sig)) {
log(" found stub wire: %s\n", RTLIL::id2cstr(wire->name));
} else {
if (!report_bits)
diff --git a/manual/PRESENTATION_Prog/my_cmd.cc b/manual/PRESENTATION_Prog/my_cmd.cc
index 381b05871..3e3cf13a0 100644
--- a/manual/PRESENTATION_Prog/my_cmd.cc
+++ b/manual/PRESENTATION_Prog/my_cmd.cc
@@ -12,7 +12,7 @@ struct MyPass : public Pass {
log("Modules in current design:\n");
for (auto mod : design->modules())
log(" %s (%zd wires, %zd cells)\n", log_id(mod),
- SIZE(mod->wires()), SIZE(mod->cells()));
+ GetSize(mod->wires()), GetSize(mod->cells()));
}
} MyPass;