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* split CodingReadme into multiple filesN. Engelhardt2021-03-221-5/+6
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* bugpoint: add runner optionZachary Snow2021-03-171-0/+3
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* verilog: Use proc memory writes in the frontend.Marcelina Kościelnicka2021-03-081-0/+5
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* Add support for memory writes in processes.Marcelina Kościelnicka2021-03-081-2/+3
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* Update command-reference-manual.texClaire Xen2021-03-041-4/+4
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* RTLIL Documentation: switch in process is optionalRobert Baruch2021-02-271-1/+1
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* Further juggles the wording of "character".Robert Baruch2020-11-251-1/+1
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* Clarifies how character encodings work.Robert Baruch2020-11-251-5/+5
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* Clarifies whitespace and eol.Robert Baruch2020-11-251-2/+6
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* Cleans up doublequotesRobert Baruch2020-11-251-2/+2
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* Clarifies use of integers, and character set.Robert Baruch2020-11-251-4/+12
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* Clarifies processes, corrects some attributesRobert Baruch2020-11-251-29/+46
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* Refactors for attributes.Robert Baruch2020-11-241-50/+50
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* Cleans up some descriptions and syntaxRobert Baruch2020-11-241-25/+43
| | | Now all rules ending in "-stmt" end in eol.
* Adds missing "end" and eol to module.Robert Baruch2020-11-221-1/+1
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* Update to Values #2Robert Baruch2020-11-221-1/+1
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* Update to Values sectionRobert Baruch2020-11-221-2/+2
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* Adds appendix on RTLIL text formatRobert Baruch2020-11-223-0/+260
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* manual: fix typo.whitequark2020-08-271-1/+1
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* Replace "ILANG" with "RTLIL" everywhere.whitequark2020-08-263-16/+14
| | | | | | | | | | The only difference between "RTLIL" and "ILANG" is that the latter is the text representation of the former, as opposed to the in-memory graph representation. This distinction serves no purpose but confuses people: it is not obvious that the ILANG backend writes RTLIL graphs. Passes `write_ilang` and `read_ilang` are provided as aliases to `write_rtlil` and `read_rtlil` for compatibility.
* Add latches to the manual.Marcelina Kościelnicka2020-06-261-42/+165
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* Add a few more gate types to the manual.Marcelina Kościelnicka2020-06-261-8/+36
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* Add new builtin FF typesMarcelina Kościelnicka2020-06-231-28/+178
| | | | | | | | | | | | | | The new types include: - FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`) - FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`) - FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`) - FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`) - FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`) - latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`) The new FF types are not actually used anywhere yet (this is left for future commits).
* Use C++11 final/override keywords.whitequark2020-06-182-4/+4
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* flatten: preserve original object names via hdlname attribute.whitequark2020-06-081-0/+7
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* Use in-tree include directory in manual buildXiretza2020-05-301-1/+4
| | | | | | | | This is basically the same issue as in tests/various/plugin.sh, which uses yosys-config to compile a plugin. `yosys-config --cxxflags` points to `$PREFIX/share/` (/usr/local/share by default), which might not exist yet or might be out of date. Building directly from the headers in ./share/ avoids this.
* Merge pull request #1885 from Xiretza/mod-rem-cellsclairexen2020-05-292-1/+24
|\ | | | | Fix modulo/remainder semantics
| * Document division and modulo cellsXiretza2020-05-281-0/+23
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| * Add flooring division operatorXiretza2020-05-281-1/+1
| | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
| * Add flooring modulo operatorXiretza2020-05-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* | Restrict RTLIL::IdString to not contain whitespace or control chars.whitequark2020-05-291-3/+6
|/ | | | | This is an existing invariant (most backends can't cope with these) but one that was not checked or documented.
* Update CHANGELOG and manual for departure from upstreamEddie Hung2020-04-271-2/+3
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* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-198/+2300
| | | | | | This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed.
* fix typo in `write_smt2` helpTeguh Hofstee2020-03-231-1/+1
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* manual: explain RTLIL::Wire::{upto,offset}.whitequark2020-02-091-0/+7
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* Merge pull request #1553 from whitequark/manual-dffxClaire Wolf2020-01-281-11/+90
|\ | | | | Document $dffe, $dffsr, $_DFFE_*, $_DFFSR_* cells
| * manual: document $dffe, $dffsr, $_DFFE_*, $_DFFSR_* cells.whitequark2019-12-051-11/+90
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* | Merge pull request #1575 from rodrigomelo9/masterEddie Hung2019-12-151-2/+2
|\ \ | | | | | | Fixed some missing "verilog_" in documentation
| * | Fixed some missing "verilog_" in documentationRodrigo Alejandro Melo2019-12-131-2/+2
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* | | Merge pull request #1577 from gromero/for-yosysEddie Hung2019-12-151-1/+1
|\ \ \ | |/ / |/| | manual: Fix text in Abstract section
| * | manual: Fix text in Abstract sectionGustavo Romero2019-12-111-1/+1
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* / manual: document behavior of many comb cells more precisely.whitequark2019-12-041-35/+56
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* Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* manual: explain the purpose of `sync always`.whitequark2019-07-021-2/+3
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* Explain exact semantics of switch and case rules in the manual.whitequark2019-06-191-0/+12
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* Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-231-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add CellTypes support for $specify2 and $specify3Clifford Wolf2019-04-231-0/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* manual: document some gates.whitequark2019-01-141-9/+11
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* manual: explain $tribuf cell.whitequark2019-01-141-0/+10
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* Fix typo in manualClifford Wolf2019-01-071-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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