| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fixed some missing "verilog_" in documentation | Rodrigo Alejandro Melo | 2019-12-13 | 1 | -2/+2 |
| * | Spell check (by Larry Doolittle) | Clifford Wolf | 2015-08-14 | 1 | -12/+12 |
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -4/+4 |
| * | Corrected spelling mistakes found by lintian | Ruben Undheim | 2014-09-06 | 1 | -3/+3 |
| * | Added RTLIL and Liberty syntax highlighting to manual | Clifford Wolf | 2013-07-25 | 1 | -1/+1 |
| * | Added Yosys Manual | Clifford Wolf | 2013-07-20 | 1 | -0/+849 |
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index : iCE40/yosys | |
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