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| author | Clifford Wolf <clifford@clifford.at> | 2015-07-02 11:14:30 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-07-02 11:14:30 +0200 |
| commit | 6c84341f22b2758181164e8d5cddd23e3589c90b (patch) | |
| tree | 0438ad9becf956e43ebf8665fee89e021b13bcdf /manual/CHAPTER_Verilog.tex | |
| parent | 053058d78167f7f1ec377fddcee8b648a5ae4138 (diff) | |
| download | yosys-6c84341f22b2758181164e8d5cddd23e3589c90b.tar.gz yosys-6c84341f22b2758181164e8d5cddd23e3589c90b.tar.bz2 yosys-6c84341f22b2758181164e8d5cddd23e3589c90b.zip | |
Fixed trailing whitespaces
Diffstat (limited to 'manual/CHAPTER_Verilog.tex')
| -rw-r--r-- | manual/CHAPTER_Verilog.tex | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/manual/CHAPTER_Verilog.tex b/manual/CHAPTER_Verilog.tex index 485b4f357..c2249d1f2 100644 --- a/manual/CHAPTER_Verilog.tex +++ b/manual/CHAPTER_Verilog.tex @@ -550,23 +550,23 @@ process $proc$<input>:1$1 switch \in2 case 1'1 assign $1\out1[0:0] $logic_not$<input>:4$2_Y - case + case assign $1\out1[0:0] \in1 end switch \in3 case 1'1 assign $0\out2[0:0] \out2 - case + case end switch \in4 case 1'1 switch \in5 case 1'1 assign $0\out3[0:0] \in6 - case + case assign $0\out3[0:0] \in7 end - case + case end sync posedge \clock update \out1 $0\out1[0:0] |