iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Add $specrule cells for $setup/$hold/$skew specify rules	Clifford Wolf	2019-04-23	1	-1/+1
*	Add CellTypes support for $specify2 and $specify3	Clifford Wolf	2019-04-23	1	-0/+4
*	manual: document some gates.	whitequark	2019-01-14	1	-9/+11
*	manual: explain $tribuf cell.	whitequark	2019-01-14	1	-0/+10
*	Fix typo in manual	Clifford Wolf	2019-01-07	1	-1/+1
*	manual: make description of $meminit ports match reality.	whitequark	2018-12-21	1	-3/+15
*	manual: fix typos.	whitequark	2018-12-20	1	-2/+2
*	manual: document $meminit cell and memory_* passes.	whitequark	2018-12-20	1	-6/+21
*	Add $allconst and $allseq cell types	Clifford Wolf	2018-02-23	1	-1/+2
*	Add $_ANDNOT_ and $_ORNOT_ gates	Clifford Wolf	2017-05-17	1	-1/+2
*	Add $live and $fair cell types, add support for s_eventually keyword	Clifford Wolf	2017-02-25	1	-1/+1
*	Add $cover cell type and SVA cover() support	Clifford Wolf	2017-02-04	1	-1/+1
*	Added $anyseq cell type	Clifford Wolf	2016-10-14	1	-1/+1
*	Added $ff and $_FF_ cell types	Clifford Wolf	2016-10-12	1	-0/+4
*	Removed $aconst cell type	Clifford Wolf	2016-08-30	1	-1/+1
*	Removed $predict again	Clifford Wolf	2016-08-28	1	-1/+1
*	Added $anyconst and $aconst	Clifford Wolf	2016-07-27	1	-1/+1
*	Added $initstate cell type and vlog function	Clifford Wolf	2016-07-21	1	-1/+1
*	After reading the SV spec, using non-standard predict() instead of expect()	Clifford Wolf	2016-07-21	1	-1/+1
*	Added basic support for $expect cells	Clifford Wolf	2016-07-13	1	-1/+1
*	Added $sop cell type and "abc -sop"	Clifford Wolf	2016-06-17	1	-0/+4
*	Added read-enable to memory model	Clifford Wolf	2015-09-25	1	-2/+6
*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14	1	-2/+2
*	Added $assume cell type	Clifford Wolf	2015-02-26	1	-1/+1
*	Added $equiv cell type	Clifford Wolf	2015-01-19	1	-1/+1
*	Added more documentation fixmes for nontrivial register cells	Clifford Wolf	2014-12-08	1	-1/+9
*	Added $lcu cell type	Clifford Wolf	2014-09-08	1	-1/+1
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	1	-6/+0
*	Added $alu cell type	Clifford Wolf	2014-08-30	1	-0/+4
*	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...	Clifford Wolf	2014-08-16	1	-0/+4
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	1	-2/+2
*	Removed old doc references to $safe_pmux	Clifford Wolf	2014-08-15	1	-4/+0
*	Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal	Clifford Wolf	2014-07-16	1	-3/+4
*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07	1	-0/+4
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	1	-0/+7
*	Added $assert cell	Clifford Wolf	2014-01-19	1	-0/+4
*	Added correct handling of $memwr priority	Clifford Wolf	2014-01-03	1	-0/+3
*	Added new cell types to manual	Clifford Wolf	2013-12-28	1	-0/+9
*	Moved common techlib files to techlibs/common	Clifford Wolf	2013-09-15	1	-2/+2
*	Added Yosys Manual	Clifford Wolf	2013-07-20	1	-0/+408