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| author | Clifford Wolf <clifford@clifford.at> | 2017-02-25 10:36:39 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2017-02-25 10:36:39 +0100 |
| commit | 5f1d0b1024981b6ede2988bf8c5812b37c87d0e9 (patch) | |
| tree | 75e48829241c9c65b5c9c7a34cc21048285ea48b /manual/CHAPTER_CellLib.tex | |
| parent | 7af9727f78263d2fc41178396791f51a680acdfa (diff) | |
| download | yosys-5f1d0b1024981b6ede2988bf8c5812b37c87d0e9.tar.gz yosys-5f1d0b1024981b6ede2988bf8c5812b37c87d0e9.tar.bz2 yosys-5f1d0b1024981b6ede2988bf8c5812b37c87d0e9.zip | |
Add $live and $fair cell types, add support for s_eventually keyword
Diffstat (limited to 'manual/CHAPTER_CellLib.tex')
| -rw-r--r-- | manual/CHAPTER_CellLib.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index 7686f5963..b2ba1fd88 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -421,7 +421,7 @@ pass. The combinatorial logic cells can be mapped to physical cells from a Liber using the {\tt abc} pass. \begin{fixme} -Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$cover}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$anyconst}, and {\tt \$anyseq} cells. +Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$live}, {\tt \$fair}, {\tt \$cover}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$anyconst}, and {\tt \$anyseq} cells. \end{fixme} \begin{fixme} |