aboutsummaryrefslogtreecommitdiffstats
path: root/manual/CHAPTER_CellLib.tex
Commit message (Expand)AuthorAgeFilesLines
* manual: document some gates.whitequark2019-01-141-9/+11
* manual: explain $tribuf cell.whitequark2019-01-141-0/+10
* Fix typo in manualClifford Wolf2019-01-071-1/+1
* manual: make description of $meminit ports match reality.whitequark2018-12-211-3/+15
* manual: fix typos.whitequark2018-12-201-2/+2
* manual: document $meminit cell and memory_* passes.whitequark2018-12-201-6/+21
* Add $allconst and $allseq cell typesClifford Wolf2018-02-231-1/+2
* Add $_ANDNOT_ and $_ORNOT_ gatesClifford Wolf2017-05-171-1/+2
* Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-251-1/+1
* Add $cover cell type and SVA cover() supportClifford Wolf2017-02-041-1/+1
* Added $anyseq cell typeClifford Wolf2016-10-141-1/+1
* Added $ff and $_FF_ cell typesClifford Wolf2016-10-121-0/+4
* Removed $aconst cell typeClifford Wolf2016-08-301-1/+1
* Removed $predict againClifford Wolf2016-08-281-1/+1
* Added $anyconst and $aconstClifford Wolf2016-07-271-1/+1
* Added $initstate cell type and vlog functionClifford Wolf2016-07-211-1/+1
* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-211-1/+1
* Added basic support for $expect cellsClifford Wolf2016-07-131-1/+1
* Added $sop cell type and "abc -sop"Clifford Wolf2016-06-171-0/+4
* Added read-enable to memory modelClifford Wolf2015-09-251-2/+6
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-2/+2
* Added $assume cell typeClifford Wolf2015-02-261-1/+1
* Added $equiv cell typeClifford Wolf2015-01-191-1/+1
* Added more documentation fixmes for nontrivial register cellsClifford Wolf2014-12-081-1/+9
* Added $lcu cell typeClifford Wolf2014-09-081-1/+1
* Removed $bu0 cell typeClifford Wolf2014-09-041-6/+0
* Added $alu cell typeClifford Wolf2014-08-301-0/+4
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-161-0/+4
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-151-2/+2
* Removed old doc references to $safe_pmuxClifford Wolf2014-08-151-4/+0
* Changed the $mem/$memwr WR_EN input to a per-data-bit enable signalClifford Wolf2014-07-161-3/+4
* Added $slice and $concat cell typesClifford Wolf2014-02-071-0/+4
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-031-0/+7
* Added $assert cellClifford Wolf2014-01-191-0/+4
* Added correct handling of $memwr priorityClifford Wolf2014-01-031-0/+3
* Added new cell types to manualClifford Wolf2013-12-281-0/+9
* Moved common techlib files to techlibs/commonClifford Wolf2013-09-151-2/+2
* Added Yosys ManualClifford Wolf2013-07-201-0/+408