iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Store command history when terminating with an error	Clifford Wolf	2017-06-20	3	-17/+31
*	Add "setundef -anyseq"	Clifford Wolf	2017-05-28	1	-12/+12
*	Enable readline and tcl in mxe builds	Clifford Wolf	2017-05-17	1	-0/+10
*	Add missing AndnotGate() and OrnotGate() declarations to rtlil.h	Clifford Wolf	2017-05-17	1	-13/+15
*	Add $_ANDNOT_ and $_ORNOT_ gates	Clifford Wolf	2017-05-17	6	-55/+94
*	Add ConstEval defaultval feature	Clifford Wolf	2017-04-05	1	-1/+8
*	Add front-end detection for *.tcl files	Clifford Wolf	2017-03-28	1	-1/+6
*	Add $live and $fair cell types, add support for s_eventually keyword	Clifford Wolf	2017-02-25	3	-1/+21
*	Fix mingw compile issue (2nd attempt)	Clifford Wolf	2017-02-23	1	-2/+2
*	Fix mingw compile issue (maybe.. I can't test it)	Clifford Wolf	2017-02-23	1	-2/+2
*	Fix eval implementation of $_NOR_	Clifford Wolf	2017-02-16	1	-1/+1
*	Add "yosys -w" for suppressing warnings	Clifford Wolf	2017-02-12	3	-11/+34
*	Add log_wire() API	Clifford Wolf	2017-02-11	2	-0/+8
*	Fix undef propagation bug in $pmux SAT model	Clifford Wolf	2017-02-05	1	-14/+4
*	Add $cover cell type and SVA cover() support	Clifford Wolf	2017-02-04	3	-1/+11
*	Fix RTLIL::Memory::start_offset initialization	Clifford Wolf	2017-01-25	1	-0/+1
*	Bugfix in RTLIL::SigSpec::remove2()	Clifford Wolf	2016-12-31	1	-3/+4
*	Simplified log_spacer() code	Clifford Wolf	2016-12-23	1	-6/+2
*	Added "yosys -W regex"	Clifford Wolf	2016-12-22	3	-2/+44
*	Added AIGER back-end to automatic back-end detection	Clifford Wolf	2016-12-21	1	-0/+2
*	Bugfix in comment handling	Clifford Wolf	2016-12-13	1	-1/+1
*	Remember global declarations and defines accross read_verilog calls	Clifford Wolf	2016-11-15	2	-1/+4
*	Some minor build fixes for Visual C	Clifford Wolf	2016-10-14	2	-1/+5
*	Added $anyseq cell type	Clifford Wolf	2016-10-14	4	-3/+19
*	Added $global_clock verilog syntax support for creating $ff cells	Clifford Wolf	2016-10-14	1	-1/+2
*	Added $ff and $_FF_ cell types	Clifford Wolf	2016-10-12	4	-1/+31
*	define PATH_MAX if not defined by limits.h	Clifford Wolf	2016-10-11	1	-0/+5
*	Improvements in assertpmux	Clifford Wolf	2016-09-07	2	-0/+19
*	Removed $aconst cell type	Clifford Wolf	2016-08-30	2	-2/+1
*	Removed $predict again	Clifford Wolf	2016-08-28	3	-11/+1
*	Fixed handling of transparent bram rd ports on ROMs	Clifford Wolf	2016-08-27	1	-0/+1
*	Added glob support to all front-ends	Clifford Wolf	2016-08-22	3	-4/+38
*	Add MSYS2-compatible build.	William D. Jones	2016-08-16	1	-2/+1
*	Use _Exit(0) on win32, always use _Exit(1) in log_error()	Clifford Wolf	2016-08-16	2	-1/+6
*	Added log_const() API	Clifford Wolf	2016-08-09	2	-0/+19
*	Use /proc/self/exe on Cygwin as well.	Yury Gribov	2016-08-08	1	-1/+1
*	Added SatGen support for $anyconst	Clifford Wolf	2016-07-27	1	-0/+22
*	Removed $predict support from SatGen	Clifford Wolf	2016-07-27	1	-9/+0
*	Added $anyconst and $aconst	Clifford Wolf	2016-07-27	2	-0/+8
*	Added "read_verilog -dump_rtlil"	Clifford Wolf	2016-07-27	2	-0/+8
*	Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()	Clifford Wolf	2016-07-25	2	-2/+2
*	Improvements in CellEdgesDatabase	Clifford Wolf	2016-07-24	2	-13/+134
*	Added CellEdgesDatabase API	Clifford Wolf	2016-07-24	2	-0/+151
*	Added satgen initstate support	Clifford Wolf	2016-07-22	1	-0/+27
*	Added $initstate cell type and vlog function	Clifford Wolf	2016-07-21	3	-3/+10
*	After reading the SV spec, using non-standard predict() instead of expect()	Clifford Wolf	2016-07-21	3	-4/+4
*	Added basic support for $expect cells	Clifford Wolf	2016-07-13	4	-8/+29
*	A few modifications after pull request comments	Ruben Undheim	2016-06-18	2	-3/+2
*	Added support for SystemVerilog packages with localparam definitions	Ruben Undheim	2016-06-18	2	-0/+4
*	Added $sop SAT model	Clifford Wolf	2016-06-17	1	-0/+82