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Author
Age
Files
Lines
*
Added "synth" command
Clifford Wolf
2014-09-14
1
-10
/
+4
*
Simplified $fa undef model
Clifford Wolf
2014-09-08
2
-14
/
+5
*
Added $lcu cell type
Clifford Wolf
2014-09-08
4
-0
/
+84
*
Added "$fa" cell type
Clifford Wolf
2014-09-08
4
-0
/
+90
*
Added $macc eval model
Clifford Wolf
2014-09-06
1
-0
/
+22
*
Added $macc SAT model
Clifford Wolf
2014-09-06
1
-0
/
+71
*
Added $macc cell type
Clifford Wolf
2014-09-06
3
-7
/
+189
*
Corrected spelling mistakes found by lintian
Ruben Undheim
2014-09-06
1
-3
/
+3
*
Removed $bu0 cell type
Clifford Wolf
2014-09-04
5
-31
/
+6
*
Using $pos models for $bu0
Clifford Wolf
2014-09-03
2
-2
/
+2
*
Fixes in $alu SAT- and eval-models
Clifford Wolf
2014-09-03
2
-6
/
+5
*
Create a default selection stack in RTLIL::Design::Design()
Clifford Wolf
2014-09-02
2
-2
/
+1
*
Small bug fixes in $not, $neg, and $shiftx models
Clifford Wolf
2014-09-02
2
-6
/
+6
*
Added ConstEval model for $alu cells
Clifford Wolf
2014-09-01
1
-0
/
+56
*
Added SAT model for $alu cells
Clifford Wolf
2014-09-01
1
-2
/
+69
*
Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...
Clifford Wolf
2014-09-01
2
-36
/
+32
*
Fixed return size of const_*() eval functions
Clifford Wolf
2014-08-31
1
-1
/
+5
*
Added RTLIL::Const::size()
Clifford Wolf
2014-08-31
1
-0
/
+2
*
Added eval model for $lut cells
Clifford Wolf
2014-08-31
1
-0
/
+26
*
Typo fixes in cell->*Param() API
Clifford Wolf
2014-08-31
1
-4
/
+4
*
Added $lut support in test_cell, techmap, satgen
Clifford Wolf
2014-08-31
2
-4
/
+57
*
Added design->scratchpad
Clifford Wolf
2014-08-30
2
-0
/
+72
*
Added $alu cell type
Clifford Wolf
2014-08-30
2
-0
/
+16
*
Fixed module->addPmux()
Clifford Wolf
2014-08-30
1
-1
/
+0
*
Added is_signed argument to SigSpec.as_int() and Const.as_int()
Clifford Wolf
2014-08-24
2
-6
/
+9
*
Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore
Clifford Wolf
2014-08-23
6
-189
/
+19
*
Changed frontend-api from FILE to std::istream
Clifford Wolf
2014-08-23
3
-13
/
+19
*
Changed backend-api from FILE to std::ostream
Clifford Wolf
2014-08-23
5
-49
/
+36
*
Added emscripten (emcc) support to build system and some build fixes
Clifford Wolf
2014-08-22
6
-10
/
+40
*
Added "plugin" command
Clifford Wolf
2014-08-22
3
-10
/
+17
*
Added mod->addGate() methods for new gate types
Clifford Wolf
2014-08-19
2
-63
/
+100
*
Fixed proc_{self,share}_dirname error handling
Clifford Wolf
2014-08-17
1
-4
/
+2
*
Improved sig.remove2() performance
Clifford Wolf
2014-08-17
1
-2
/
+11
*
Added stackmap<> container
Clifford Wolf
2014-08-17
2
-2
/
+109
*
Renamed toposort.h to utils.h
Clifford Wolf
2014-08-17
1
-0
/
+0
*
Added module->uniquify()
Clifford Wolf
2014-08-16
2
-0
/
+25
*
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...
Clifford Wolf
2014-08-16
4
-19
/
+152
*
Added CellTypes::cell_evaluable()
Clifford Wolf
2014-08-16
1
-31
/
+37
*
Added log_spacer()
Clifford Wolf
2014-08-16
3
-2
/
+20
*
Renamed $lut ports to follow A-Y naming scheme
Clifford Wolf
2014-08-15
2
-6
/
+5
*
Renamed $_INV_ cell type to $_NOT_
Clifford Wolf
2014-08-15
4
-7
/
+7
*
More idstring sort_by_* helpers and fixed tpl ordering in techmap
Clifford Wolf
2014-08-15
1
-1
/
+13
*
Added Frontend "+/" filename syntax for files from proc_share_dir
Clifford Wolf
2014-08-15
1
-1
/
+4
*
Added RTLIL::SigSpec::to_sigbit_map()
Clifford Wolf
2014-08-14
2
-0
/
+17
*
Added sig.{replace,remove,extract} variants for std::{map,set} pattern
Clifford Wolf
2014-08-14
2
-25
/
+64
*
Added module->ports
Clifford Wolf
2014-08-14
3
-2
/
+13
*
Refactoring of CellType class
Clifford Wolf
2014-08-14
2
-145
/
+111
*
RIP $safe_pmux
Clifford Wolf
2014-08-14
5
-24
/
+9
*
Fixed SigBit(RTLIL::Wire *wire) constructor
Clifford Wolf
2014-08-12
1
-1
/
+1
*
Another build fix by americanrouter (via reddit)
Clifford Wolf
2014-08-11
1
-0
/
+3
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