| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | | Added Wrappers for: | Benedikt Tutzer | 2018-08-13 | 3 | -142/+2923 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -IdString -Const -CaseRule -SwitchRule -SyncRule -Process -SigChunk -SigBit -SigSpec With all their member functions as well as the remaining member functions for Cell, Wire, Module and Design and static functions of rtlil.h | |||||
| | | * | | Saving id and pointer to c++ object. Object is valid only if both id and ↵ | Benedikt Tutzer | 2018-08-01 | 1 | -8/+29 | |
| | | | | | | | | | | | | | | | | | pointer match the pair saved in the corresponding map in kernel/rtlil.cc. Otherwise, the object was destroyed in c++ and should not be accessed any more | |||||
| | | * | | Setup is called automatically when the module is loaded, shutdown when ↵ | Benedikt Tutzer | 2018-08-01 | 1 | -16/+19 | |
| | | | | | | | | | | | | | | | | | python exits | |||||
| | | * | | Cleaned up comments | Benedikt Tutzer | 2018-08-01 | 1 | -9/+3 | |
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| | | * | | Added Monitor class that can monitor all changes in a Design or in a Module | Benedikt Tutzer | 2018-07-10 | 1 | -0/+119 | |
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| | | * | | added destructors for wires and cells | Benedikt Tutzer | 2018-07-10 | 2 | -1/+16 | |
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| | | * | | removed debug output | Benedikt Tutzer | 2018-07-09 | 1 | -1/+0 | |
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| | | * | | commands can now be run on arbitrary designs, not only on the active one | Benedikt Tutzer | 2018-07-09 | 1 | -0/+10 | |
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| | | * | | multiple designs can now exist independent from each other. ↵ | Benedikt Tutzer | 2018-07-09 | 3 | -45/+118 | |
| | | | | | | | | | | | | | | | | | Cells/Wires/Modules can now move to a different parent without referencing issues | |||||
| | | * | | Introduced namespace and removed class-prefixes to increase readability | Benedikt Tutzer | 2018-06-28 | 1 | -163/+165 | |
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| | | * | | changed references from hash-ids to IdString names | Benedikt Tutzer | 2018-06-28 | 1 | -64/+32 | |
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| | | * | | added wrappers for Design, Modules, Cells and Wires | Benedikt Tutzer | 2018-06-25 | 1 | -0/+244 | |
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| * | | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-20 | 2 | -3/+6 | |
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| | * | | | Add "wbflip" command | Clifford Wolf | 2019-04-20 | 2 | -3/+6 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | Ignore 'whitebox' attr in flatten with "-wb" option | Eddie Hung | 2019-04-18 | 1 | -2/+2 | |
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| * | | | | Ignore 'whitebox' attr in flatten with "-wb" option | Eddie Hung | 2019-04-18 | 1 | -2/+2 | |
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| * | | | | Merge remote-tracking branch 'origin/clifford/whitebox' into xaig | Eddie Hung | 2019-04-18 | 2 | -3/+7 | |
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| | * | | | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 2 | -3/+7 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | Merge branch 'master' into xaig | Eddie Hung | 2019-04-08 | 7 | -27/+151 | |
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| | * | | | Add "read_ilang -lib" | Clifford Wolf | 2019-04-05 | 2 | -0/+25 | |
| | | |/ | |/| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals | Clifford Wolf | 2019-03-23 | 2 | -1/+9 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Add fmcombine pass | Clifford Wolf | 2019-03-15 | 2 | -17/+32 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Add hashlib "<container>::element(int n)" methods | Clifford Wolf | 2019-03-14 | 1 | -0/+6 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Fix a bug in handling quotes in multi-cmd lines in Yosys scripts | Clifford Wolf | 2019-03-12 | 1 | -1/+7 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Improve determinism of IdString DB for similar scripts | Clifford Wolf | 2019-03-11 | 4 | -5/+67 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Add ENABLE_GLOB Makefile switch | Clifford Wolf | 2019-03-11 | 1 | -3/+5 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-02-26 | 1 | -2/+16 | |
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| | * | | Merge pull request #819 from YosysHQ/clifford/optd | Clifford Wolf | 2019-02-22 | 1 | -2/+16 | |
| | |\ \ | | | | | | | | | Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior | |||||
| | | * | | Rename "yosys -U" to "yosys -P" to avoid confusion about "undefine" | Clifford Wolf | 2019-02-21 | 1 | -3/+3 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior | Clifford Wolf | 2019-02-21 | 1 | -2/+16 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | Add IdString::ends_with() | Eddie Hung | 2019-02-26 | 1 | -0/+6 | |
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| * | | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-02-21 | 1 | -0/+3 | |
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| | * | | | Add FF support to wreduce | Clifford Wolf | 2019-02-20 | 1 | -0/+3 | |
| | |/ / | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * / / | Refactor kernel/cost.h definition into cost.cc | Eddie Hung | 2019-02-08 | 2 | -49/+77 | |
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| * | | Add optional nullstr argument to log_id() | Clifford Wolf | 2019-01-15 | 1 | -1/+3 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 2 | -2/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually. | |||||
| * | | proc_clean: remove any empty cases if all cases use all-def compare. | whitequark | 2018-12-23 | 2 | -0/+14 | |
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| * | | tcl: add support for passing arguments to scripts. | whitequark | 2018-12-20 | 1 | -7/+18 | |
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| * | | Improve ConstEval error handling for non-eval cell types | Clifford Wolf | 2018-11-29 | 2 | -9/+19 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Avoid assert when label is an empty string | Jon Burgess | 2018-10-28 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Calling back() on an empty string is not allowed and triggers an assert with recent gcc: $ cd manual/PRESENTATION_Intro $ ../../yosys counter.ys ... /usr/include/c++/8/bits/basic_string.h:1136: std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::back() [with _CharT = char; _Traits = std::char_traits<char>; _Alloc = std::allocator<char>; std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference = char&]: Assertion '!empty()' failed. 802 if (label.back() == ':' && GetSize(label) > 1) (gdb) p label $1 = "" | |||||
| * | | fix unhandled std::out_of_range when calling yosys with 3-character argument | whentze | 2018-10-22 | 1 | -2/+2 | |
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| * | | Documentation improvements etc. | Ruben Undheim | 2018-10-13 | 1 | -3/+1 | |
| | | | | | | | | | | | | | | | | | | | - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport) | |||||
| * | | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 2 | -2/+2 | |
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| * | | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 2 | -0/+17 | |
| | | | | | | | | | This time doing the changes mostly in AST before RTLIL generation | |||||
| * | | Fix IdString M in setup_stdcells() | Adrian Wheeldon | 2018-10-04 | 1 | -1/+1 | |
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| * | | Fix Cygwin build and document needed packages | Miodrag Milanovic | 2018-09-19 | 1 | -1/+1 | |
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| * | | Merge pull request #591 from hzeller/virtual-override | Clifford Wolf | 2018-08-15 | 8 | -32/+31 | |
| |\ \ | | | | | | | Consistent use of 'override' for virtual methods in derived classes. | |||||
| | * | | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 8 | -32/+31 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | |||||
| * | | | Map .eblif extension as blif. | litghost | 2018-08-13 | 1 | -0/+2 | |
| |/ / | | | | | | | Signed-off-by: litghost <537074+litghost@users.noreply.github.com> | |||||
| * / | Provide source-location logging. | Henner Zeller | 2018-07-19 | 2 | -44/+45 | |
| |/ | | | | | | | | o Provide log_file_warning() and log_file_error() that prefix the log message with <filename>:<lineno>: to be easily picked up by IDEs that need to step through errors. o Simplify some duplicate logging code in kernel/log.cc o Use the new log functions in genrtlil. | |||||
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index : iCE40/yosys | |
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