index
:
iCE40/yosys
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
kernel
Commit message (
Expand
)
Author
Age
Files
Lines
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
5
-17
/
+17
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
5
-27
/
+27
*
Changed more code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
2
-7
/
+23
*
Changed a lot of code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
2
-0
/
+43
*
Added support for here documents
Clifford Wolf
2014-07-26
3
-18
/
+63
*
Added RTLIL::Cell::has(portname)
Clifford Wolf
2014-07-26
3
-8
/
+14
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
1
-11
/
+11
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
5
-179
/
+179
*
Added some missing "const" in rtlil.h
Clifford Wolf
2014-07-26
2
-9
/
+9
*
Added RTLIL::Module::connections()
Clifford Wolf
2014-07-26
2
-0
/
+6
*
Added RTLIL::Module::connect(const RTLIL::SigSig&)
Clifford Wolf
2014-07-26
2
-0
/
+6
*
Automatically pack SigSpec on copy/assign
Clifford Wolf
2014-07-26
2
-17
/
+63
*
Added new RTLIL::Cell port access methods
Clifford Wolf
2014-07-26
2
-0
/
+71
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
6
-190
/
+211
*
Added copy-constructor-like module->addCell(name, other) method
Clifford Wolf
2014-07-26
2
-8
/
+12
*
Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
2
-4
/
+54
*
Added RTLIL::SigSpec is_chunk()/as_chunk() API
Clifford Wolf
2014-07-25
2
-0
/
+20
*
Disabled cover() for non-linux builds
Clifford Wolf
2014-07-25
2
-2
/
+3
*
Fixed typo in cover id
Clifford Wolf
2014-07-25
1
-1
/
+1
*
Replaced more old SigChunk programming patterns
Clifford Wolf
2014-07-24
4
-11
/
+26
*
Added cover_list() API
Clifford Wolf
2014-07-24
2
-2
/
+46
*
Added "cover" command
Clifford Wolf
2014-07-24
4
-32
/
+57
*
Some improvements in SigSpec packing/unpacking and checking
Clifford Wolf
2014-07-24
1
-8
/
+29
*
Now using a dedicated ELF section for all coverage counters
Clifford Wolf
2014-07-24
3
-26
/
+21
*
Small changes regarding cover() and check() in SigSpec
Clifford Wolf
2014-07-24
2
-10
/
+9
*
Added support for YOSYS_COVER_FILE env variable
Clifford Wolf
2014-07-24
2
-3
/
+12
*
Added cover() calls to RTLIL::SigSpec methods
Clifford Wolf
2014-07-24
1
-5
/
+93
*
Added support for YOSYS_COVER_DIR env variable
Clifford Wolf
2014-07-24
1
-0
/
+26
*
Added cover() API
Clifford Wolf
2014-07-24
2
-0
/
+35
*
Added hashing to RTLIL::SigSpec relational and equal operators
Clifford Wolf
2014-07-23
2
-17
/
+71
*
Disabled RTLIL::SigSpec::check() in release builds
Clifford Wolf
2014-07-23
1
-0
/
+2
*
Fixed release build
Clifford Wolf
2014-07-23
1
-0
/
+2
*
Added RTLIL::SigSpec::repeat()
Clifford Wolf
2014-07-23
2
-0
/
+10
*
Removed RTLIL::SigSpec::optimize()
Clifford Wolf
2014-07-23
3
-115
/
+9
*
Turned RTLIL::SigSpec::optimize() to a no-op: a packed SigSpec is now always ...
Clifford Wolf
2014-07-23
1
-7
/
+42
*
Removed RTLIL::SigSpec::expand() method
Clifford Wolf
2014-07-23
5
-200
/
+86
*
Fixed all users of SigSpec::chunks_rw() and removed it
Clifford Wolf
2014-07-23
1
-2
/
+2
*
Replaced RTLIL::SigSpec::operator!=() with inline version
Clifford Wolf
2014-07-23
2
-8
/
+1
*
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
Clifford Wolf
2014-07-23
3
-22
/
+14
*
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
Clifford Wolf
2014-07-23
2
-18
/
+4
*
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3
Clifford Wolf
2014-07-23
2
-2
/
+40
*
Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&)
Clifford Wolf
2014-07-23
2
-6
/
+6
*
SigSpec refactoring: More cleanups of old SigSpec use pattern
Clifford Wolf
2014-07-22
2
-55
/
+50
*
SigSpec refactoring: Added RTLIL::SigSpecIterator
Clifford Wolf
2014-07-22
1
-6
/
+28
*
SigSpec refactoring: added RTLIL::SigSpec::operator[]
Clifford Wolf
2014-07-22
1
-1
/
+4
*
SigSpec refactoring: rewrote some RTLIL::SigSpec methods to use unpacked form
Clifford Wolf
2014-07-22
1
-182
/
+113
*
Removed RTLIL::SigChunk::compare()
Clifford Wolf
2014-07-22
2
-25
/
+5
*
SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api
Clifford Wolf
2014-07-22
2
-18
/
+135
*
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...
Clifford Wolf
2014-07-22
4
-7
/
+7
*
SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only
Clifford Wolf
2014-07-22
1
-2
/
+1
[next]