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* Small bug fixes in $not, $neg, and $shiftx modelsClifford Wolf2014-09-022-6/+6
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* Added ConstEval model for $alu cellsClifford Wolf2014-09-011-0/+56
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* Added SAT model for $alu cellsClifford Wolf2014-09-011-2/+69
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* Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵Clifford Wolf2014-09-012-36/+32
| | | | RTLIL::SigChunk::data
* Fixed return size of const_*() eval functionsClifford Wolf2014-08-311-1/+5
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* Added RTLIL::Const::size()Clifford Wolf2014-08-311-0/+2
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* Added eval model for $lut cellsClifford Wolf2014-08-311-0/+26
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* Typo fixes in cell->*Param() APIClifford Wolf2014-08-311-4/+4
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* Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-312-4/+57
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* Added design->scratchpadClifford Wolf2014-08-302-0/+72
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* Added $alu cell typeClifford Wolf2014-08-302-0/+16
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* Fixed module->addPmux()Clifford Wolf2014-08-301-1/+0
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* Added is_signed argument to SigSpec.as_int() and Const.as_int()Clifford Wolf2014-08-242-6/+9
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* Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymoreClifford Wolf2014-08-236-189/+19
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* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-233-13/+19
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* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-235-49/+36
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* Added emscripten (emcc) support to build system and some build fixesClifford Wolf2014-08-226-10/+40
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* Added "plugin" commandClifford Wolf2014-08-223-10/+17
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* Added mod->addGate() methods for new gate typesClifford Wolf2014-08-192-63/+100
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* Fixed proc_{self,share}_dirname error handlingClifford Wolf2014-08-171-4/+2
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* Improved sig.remove2() performanceClifford Wolf2014-08-171-2/+11
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* Added stackmap<> containerClifford Wolf2014-08-172-2/+109
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* Renamed toposort.h to utils.hClifford Wolf2014-08-171-0/+0
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* Added module->uniquify()Clifford Wolf2014-08-162-0/+25
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* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵Clifford Wolf2014-08-164-19/+152
| | | | $_OAI4_
* Added CellTypes::cell_evaluable()Clifford Wolf2014-08-161-31/+37
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* Added log_spacer()Clifford Wolf2014-08-163-2/+20
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* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-152-6/+5
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* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-154-7/+7
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* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-151-1/+13
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* Added Frontend "+/" filename syntax for files from proc_share_dirClifford Wolf2014-08-151-1/+4
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* Added RTLIL::SigSpec::to_sigbit_map()Clifford Wolf2014-08-142-0/+17
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* Added sig.{replace,remove,extract} variants for std::{map,set} patternClifford Wolf2014-08-142-25/+64
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* Added module->portsClifford Wolf2014-08-143-2/+13
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* Refactoring of CellType classClifford Wolf2014-08-142-145/+111
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* RIP $safe_pmuxClifford Wolf2014-08-145-24/+9
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* Fixed SigBit(RTLIL::Wire *wire) constructorClifford Wolf2014-08-121-1/+1
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* Another build fix by americanrouter (via reddit)Clifford Wolf2014-08-111-0/+3
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* Fixed build with gcc-4.6Clifford Wolf2014-08-073-3/+11
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* Added support for truncating of wires to wreduce passClifford Wolf2014-08-053-8/+53
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* Added RTLIL::IdString::in(...)Clifford Wolf2014-08-041-5/+18
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* Added query() API to ModIndexClifford Wolf2014-08-031-8/+46
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* Added ID() macro for static IdStringsClifford Wolf2014-08-031-0/+3
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* Fixed a va_list corruption in logv_error()Clifford Wolf2014-08-021-4/+3
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* Bugfix in "techmap -extern"Clifford Wolf2014-08-021-10/+16
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* Removed at() method from RTLIL::IdStringClifford Wolf2014-08-022-7/+6
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* No implicit conversion from IdString to anything elseClifford Wolf2014-08-024-22/+22
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* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-023-17/+31
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* Limit size of log_signal buffer to 100 elementsClifford Wolf2014-08-022-2/+9
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* Improvements in new RTLIL::IdString implementationClifford Wolf2014-08-025-33/+65
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