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* Fix unused param warning with ENABLE_NDEBUG.Marcelina Kościelnicka2021-12-121-1/+1
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* sta: very crude static timing analysis passLofty2021-11-251-0/+3
| | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com>
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-251-0/+1
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
* Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-251-1/+1
| | | | | This will enable other features to use same core logic for replacing an existing AstModule with a newly elaborated version.
* Change implicit conversions from bool to Sig* to explicit.Marcelina Kościelnicka2021-10-211-2/+2
| | | | Also fixes some completely broken code in extract_reduce.
* Add $aldff and $aldffe: flip-flops with async load.Marcelina Kościelnicka2021-10-021-0/+6
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* Add additional check to SigSpecClaire Xenia Wolf2021-09-101-2/+2
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Generate an RTLIL representation of bind constructsRupert Swarbrick2021-08-131-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | This code now takes the AST nodes of type AST_BIND and generates a representation in the RTLIL for them. This is a little tricky, because a binding of the form: bind baz foo_t foo_i (.arg (1 + bar)); means "make an instance of foo_t called foo_i, instantiate it inside baz and connect the port arg to the result of the expression 1+bar". Of course, 1+bar needs a cell for the addition. Where should that cell live? With this patch, the Binding structure that represents the construct is itself an AST::AstModule module. This lets us put the adder cell inside it. We'll pull the contents out and plonk them into 'baz' when we actually do the binding operation as part of the hierarchy pass. Of course, we don't want RTLIL::Binding to contain an AST::AstModule (since kernel code shouldn't depend on a frontend), so we define RTLIL::Binding as an abstract base class and put the AST-specific code into an AST::Binding subclass. This is analogous to the AST::AstModule class.
* rtlil: Make Process handling more uniform with Cell and Wire.Marcelina Kościelnicka2021-07-121-2/+14
| | | | | | - add a backlink to module from Process - make constructor and destructor protected, expose Module functions to add and remove processes
* opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits.Marcelina Kościelnicka2021-06-091-0/+2
| | | | | The previous code, in addition to being needlessly limitted to 32 bits in the first place, also had UB for the 31th bit (doing 1 << 31).
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* kernel/rtlil: Extract some helpers for checking memory cell types.Marcelina Kościelnicka2021-05-221-0/+3
| | | | | | There will soon be more (versioned) memory cells, so handle passes that only care if a cell is memory-related by a simple helper call instead of a hardcoded list.
* rtlil: add const accessors for modules, wires, and cellsZachary Snow2021-03-251-0/+10
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* blackbox: Include whiteboxed modulesgatecat2021-03-171-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Replace assert in get_reference with more useful error messageLofty2021-03-171-1/+2
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* Add support for memory writes in processes.Marcelina Kościelnicka2021-03-081-0/+21
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* Remove a few functions that, in fact, did not exist in the first place.Marcelina Kościelnicka2021-03-061-2/+0
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* int -> boolRobert Baruch2021-02-231-2/+2
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* Adds is_wire to SigBit and SigChunkRobert Baruch2021-02-231-0/+3
| | | Useful for PYOSYS because Python can't easily check wire against NULL.
* verilog: significant block scoping improvementsZachary Snow2021-01-311-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
* kernel: make IdString::isPublic() const.whitequark2020-12-121-1/+1
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* add IdString::isPublic()N. Engelhardt2020-09-031-0/+2
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* Add add* functions for the new FF typesMarcelina Kościelnicka2020-06-231-0/+20
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* Merge pull request #2177 from boqwxp/dict-iterator-jumpwhitequark2020-06-211-0/+23
|\ | | | | hashlib, rtlil: Add `operator+()` and `operator+=()` to `dict` iterators
| * hashlib, rtlil: Add `operator+=()` to `dict<>::iterator` and ↵Alberto Gonzalez2020-06-191-0/+23
| | | | | | | | `dict<>::const_iterator` and add `operator+()` and `operator+=()` to `ObjIterator`.
* | rtlil: Add `Design::select()` for selecting whole modules.Alberto Gonzalez2020-06-191-0/+7
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* RTLIL: add Module::addProcess, use it in Module::cloneInto. NFC.whitequark2020-06-091-0/+2
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* flatten: preserve original object names via hdlname attribute.whitequark2020-06-081-0/+3
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* Merge pull request #2105 from whitequark/split-flatten-off-techmapclairexen2020-06-081-0/+2
|\ | | | | Split `flatten` from `techmap` and simplify it
| * RTLIL: factor out RTLIL::Module::addMemory. NFC.whitequark2020-06-041-0/+2
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* | Merge pull request #2006 from jersey99/signed-in-rtlil-wirewhitequark2020-06-041-1/+1
|\ \ | | | | | | Preserve 'signed'-ness of a verilog wire through RTLIL
| * | Preserve 'signed'-ness of a verilog wire through RTLILVamsi K Vytla2020-04-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now: RTLIL::wire holds an is_signed field. This is exported in JSON backend This is exported via dump_rtlil command This is read in via ilang_parser
* | | Merge pull request #2070 from hackfin/masterN. Engelhardt2020-06-041-6/+3
|\ \ \ | |_|/ |/| | Pyosys API: idict type handling
| * | idict handling in wrapperMartin2020-05-191-6/+3
| |/ | | | | | | | | - Also, re-applied no-line-break workaround to rtlil.h to make parser catch all methods.
* | Merge pull request #1885 from Xiretza/mod-rem-cellsclairexen2020-05-291-0/+10
|\ \ | | | | | | Fix modulo/remainder semantics
| * | Add comments for mod/div semantics to rtlil.hXiretza2020-05-281-0/+4
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| * | Add flooring division operatorXiretza2020-05-281-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
| * | Add flooring modulo operatorXiretza2020-05-281-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* | | Merge pull request #2092 from whitequark/rtlil-no-space-controlclairexen2020-05-291-3/+5
|\ \ \ | |/ / |/| | Restrict RTLIL::IdString to not contain whitespace or control chars
| * | Restrict RTLIL::IdString to not contain whitespace or control chars.whitequark2020-05-291-3/+5
| |/ | | | | | | | | This is an existing invariant (most backends can't cope with these) but one that was not checked or documented.
* | Merge pull request #2088 from rswarbrick/count-atwhitequark2020-05-281-2/+8
|\ \ | | | | | | Minor optimisation in Module::wire() and Module::cell()
| * | Minor optimisation in Module::wire() and Module::cell()Rupert Swarbrick2020-05-261-2/+8
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing code does a search to figure out whether id is in the dict (with the call to count()), and then looks it up again to get the result (with the call to at()). This version calls find() instead, avoiding the double lookup. Code size increases slightly (6kb). I think this is because the contents of find() are getting inlined, and then inlined into lots of the callsites for cell() and wire(). Looking at the compiled code before this patch, you just get a (non-inlined) call to count() followed by a call to at(). After the patch, the contents of find() have been inlined (so you see do_hash, then do_lookup). The result for each function is about 30 bytes / 40% bigger, which presumably also enlarges call-sites that inline it.
* | Merge pull request #2086 from rswarbrick/sigbitwhitequark2020-05-281-2/+1
|\ \ | | | | | | Use default copy constructor for RTLIL::SigBit
| * | Use default copy constructor for RTLIL::SigBitRupert Swarbrick2020-05-261-2/+1
| |/ | | | | | | | | | | | | | | | | | | | | There was a handwritten copy constructor, which I'm not sure was actually legal C++ (it unconditionally read from the 'data' member of a union, which wouldn't have been written if wire was true). It was also a bit less efficient than the constructor you get from the compiler by default (which is allowed to just copy the memory). This gives a marginal (~0.25%) decrease in code size when compiled with GCC 9.3.
* / Use c_str(), not str() for IdString/std::string == and != operatorsRupert Swarbrick2020-05-261-2/+2
|/ | | | | | | | | | | | | | | These operators work by fetching the string from the global string table and then comparing with the std::string that was passed in as rhs. Using str() means that we create a std::string (strlen; malloc; memcpy), compare for equality (another memcmp if they have the same length) and then finally free the string. Using c_str() means that we pass the const char* straight to std::string's equality operator. This ends up as a call to std::string::compare (the const char* flavour), which is essentially strcmp.
* ilang, ast: Store parameter order and default value information.Marcelina Kościelnicka2020-04-211-1/+2
| | | | Fixes #1819, #1820.
* rtlil: add AttrObject::has_attribute.whitequark2020-04-161-0/+2
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* rtlil: add AttrObject::{get,set}_string_attribute.whitequark2020-04-161-2/+9
| | | | And make {get,set}_src_attribute use those functions.
* Merge pull request #1858 from YosysHQ/eddie/fix1856Eddie Hung2020-04-091-1/+1
|\ | | | | kernel: include "kernel/constids.inc"
| * kernel: include "kernel/constids.inc" instead of "constids.inc"Eddie Hung2020-04-091-1/+1
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