| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fixes for some of clang scan-build detected issues | Miodrag Milanovic | 2023-01-17 | 1 | -1/+1 |
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| * | fstdata: Update past_data before end_time callback | Jannis Harder | 2022-11-07 | 1 | -0/+1 |
| | | | | | Required to make the '-at' parameter work. | ||||
| * | fstdata: Handle square/angle bracket replacemnt, change memory handling | Jannis Harder | 2022-11-07 | 1 | -8/+19 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When writing VCDs smtbmc replaces square brackets with angle brackets to avoid the issues with VCD readers misinterpreting such signal names. For memory addresses it also uses angle brackets and hexadecimal addresses, while other tools will use square brackets and decimal addresses. Previously the code handled both forms of memory addresses, assuming that any signal that looks like a memory address is a memory address. This is not the case when the user uses regular signals whose names include square brackets _or_ when the verific frontend generates such names to represent various constructs. With this change all angular brackets are turned into square brackets when reading the trace _and_ when performing a signal lookup. This means no matter which kind of brackets are used in the design or in the VCD signals will be matched. This will not handle multiple signals that are the same apart from replacing square/angle brackets, but this will cause issues during the VCD writing of smtbmc already. It still uses the distinction between square and angle brackets for memories to decide whether the address is hex or decimal, but even if something looks like a memory and is added to the `memory_to_handle` data, the plain signal added to `name_to_handle` is used as-is, without rewriting the address. This last change is needed to successfully match verific generated signal names that look like memory addresses while keeping memories working at the same time. It may cause regressions when VCD generation was done with a design that had memories but simulation is done with a design where the memories were mapped to registers. This seems like an unusual setup, but could be worked around with some further changes should this be required. | ||||
| * | Observe $TMPDIR variable when creating tmp files | Mohamed A. Bamakhrama | 2022-05-27 | 1 | -1/+1 |
| | | | | | | | | | | POSIX defines $TMPDIR as containing the pathname of the directory where programs can create temporary files. On most systems, this variable points to "/tmp". However, on some systems it can point to a different location. Without respecting this variable, yosys fails to run on such systems. Signed-off-by: Mohamed A. Bamakhrama <mohamed@alumni.tum.de> | ||||
| * | Handle possible non-memory indexed data | Miodrag Milanovic | 2022-05-06 | 1 | -8/+10 |
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| * | map memory location to wire value, if memory is converted to FFs | Miodrag Milanovic | 2022-05-04 | 1 | -0/+4 |
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| * | Start restoring memory state from VCD/FST | Miodrag Milanovic | 2022-05-04 | 1 | -1/+31 |
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| * | Ignore change on last edge | Miodrag Milanovic | 2022-04-22 | 1 | -4/+5 |
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| * | Proper scope naming from FST | Miodrag Milanovic | 2022-03-30 | 1 | -8/+4 |
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| * | More verbose warnings | Miodrag Milanovic | 2022-03-18 | 1 | -1/+2 |
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| * | Recognize registers and set initial state for them in tb | Miodrag Milanovic | 2022-03-16 | 1 | -0/+1 |
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| * | VCD reader support by using external tool | Miodrag Milanovic | 2022-02-28 | 1 | -0/+19 |
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| * | Fix for last clock edge data | Miodrag Milanovic | 2022-02-25 | 1 | -0/+1 |
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| * | Changed error message | Miodrag Milanovic | 2022-02-18 | 1 | -1/+1 |
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| * | Add support for various ff/latch cells simulation | Miodrag Milanovic | 2022-02-16 | 1 | -98/+43 |
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| * | Error detection for co-simulation | Miodrag Milanovic | 2022-02-04 | 1 | -0/+2 |
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| * | bug fix and cleanups | Miodrag Milanovic | 2022-02-04 | 1 | -1/+1 |
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| * | Cleanup | Miodrag Milanovic | 2022-01-31 | 1 | -1/+0 |
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| * | Display simulation time data | Miodrag Milanovic | 2022-01-31 | 1 | -1/+21 |
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| * | ignore not found private signals | Miodrag Milanovic | 2022-01-28 | 1 | -2/+1 |
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| * | preserve VCD mangled names | Miodrag Milanovic | 2022-01-28 | 1 | -1/+3 |
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| * | detect edges even when x | Miodrag Milanovic | 2022-01-28 | 1 | -2/+2 |
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| * | cleanup | Miodrag Milanovic | 2022-01-28 | 1 | -13/+1 |
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| * | Do actual compare | Miodrag Milanovic | 2022-01-28 | 1 | -65/+41 |
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| * | Add more options and time handling | Miodrag Milanovic | 2022-01-28 | 1 | -0/+1 |
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| * | Add fstdata helper class | Miodrag Milanovic | 2022-01-26 | 1 | -0/+265 |
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