Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Improve ConstEval error handling for non-eval cell types | Clifford Wolf | 2018-11-29 | 1 | -2/+7 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add ConstEval defaultval feature | Clifford Wolf | 2017-04-05 | 1 | -1/+8 |
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* | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -2/+2 |
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* | Renamed SIZE() to GetSize() because of name collision on Win32 | Clifford Wolf | 2014-10-10 | 1 | -10/+10 |
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* | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -0/+4 |
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* | Simplified $fa undef model | Clifford Wolf | 2014-09-08 | 1 | -0/+4 |
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* | Added $lcu cell type | Clifford Wolf | 2014-09-08 | 1 | -0/+37 |
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* | Added "$fa" cell type | Clifford Wolf | 2014-09-08 | 1 | -0/+25 |
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* | Added $macc eval model | Clifford Wolf | 2014-09-06 | 1 | -0/+22 |
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* | Fixes in $alu SAT- and eval-models | Clifford Wolf | 2014-09-03 | 1 | -2/+2 |
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* | Added ConstEval model for $alu cells | Clifford Wolf | 2014-09-01 | 1 | -0/+56 |
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* | Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵ | Clifford Wolf | 2014-08-16 | 1 | -1/+16 |
| | | | | $_OAI4_ | ||||
* | RIP $safe_pmux | Clifford Wolf | 2014-08-14 | 1 | -5/+2 |
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* | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -8/+8 |
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* | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -4/+4 |
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* | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
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* | Added RTLIL::Cell::has(portname) | Clifford Wolf | 2014-07-26 | 1 | -4/+4 |
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* | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -9/+9 |
| | | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' | ||||
* | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -9/+9 |
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* | Replaced more old SigChunk programming patterns | Clifford Wolf | 2014-07-24 | 1 | -3/+3 |
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* | Removed RTLIL::SigSpec::expand() method | Clifford Wolf | 2014-07-23 | 1 | -5/+2 |
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* | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵ | Clifford Wolf | 2014-07-22 | 1 | -1/+1 |
| | | | | created interim RTLIL::SigSpec::chunks_rw() | ||||
* | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -9/+9 |
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* | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -9/+9 |
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* | Fixed SAT and ConstEval undef handling for $pmux and $safe_pmux | Clifford Wolf | 2014-01-03 | 1 | -4/+6 |
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* | Fixed handling of undef values in MUX select input in ConstEval | Clifford Wolf | 2013-11-06 | 1 | -32/+58 |
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* | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+198 |