| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | Add "read -verific" and "read -noverific" | Clifford Wolf | 2019-03-27 | 1 | -6/+28 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Fix "verific -extnets" for more complex situations | Clifford Wolf | 2019-03-26 | 1 | -15/+71 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Fix mem2reg handling of memories with upto data ports, fixes #888 | Clifford Wolf | 2019-03-21 | 1 | -1/+10 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Improve "read_verilog -dump_vlog[12]" handling of upto ranges | Clifford Wolf | 2019-03-21 | 1 | -3/+6 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Improve read_verilog debug output capabilities | Clifford Wolf | 2019-03-21 | 3 | -15/+42 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Merge https://github.com/YosysHQ/yosys into read_aiger | Eddie Hung | 2019-03-19 | 8 | -110/+348 | |
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| | | * | fix local name resolution in prefix constructs | Zachary Snow | 2019-03-18 | 1 | -1/+5 | |
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| | | * | Improve handling of "full_case" attributes | Clifford Wolf | 2019-03-14 | 1 | -0/+9 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | Improve handling of memories used in mem index expressions on LHS of an ↵ | Clifford Wolf | 2019-03-12 | 1 | -5/+16 | |
| | | | | | | | | | | | | | | | | | | | assignment Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | Remove outdated "blocking assignment to memory" warning | Clifford Wolf | 2019-03-12 | 1 | -10/+0 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867 | Clifford Wolf | 2019-03-12 | 1 | -6/+8 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | Fix handling of cases that look like sva labels, fixes #862 | Clifford Wolf | 2019-03-10 | 2 | -92/+66 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | Merge pull request #858 from YosysHQ/clifford/svalabels | Clifford Wolf | 2019-03-09 | 5 | -56/+201 | |
| | | |\ | | | | | | | | | Add support for using SVA labels in yosys-smtbmc console output | |||||
| | | | * | Also add support for labels on sva module items, fixes #699 | Clifford Wolf | 2019-03-08 | 2 | -44/+113 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | | * | Add support for SVA labels in read_verilog | Clifford Wolf | 2019-03-07 | 3 | -26/+89 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | | * | Add hack for handling SVA labels via Verific | Clifford Wolf | 2019-03-07 | 1 | -1/+14 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | Update help message for -chparam | Eddie Hung | 2019-03-09 | 1 | -1/+2 | |
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| | | * | | Add -chparam option to verific command | Eddie Hung | 2019-03-09 | 1 | -2/+18 | |
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| | | * | | Fix spelling | Eddie Hung | 2019-03-09 | 1 | -1/+1 | |
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| | | * | | Fix handling of task output ports in clocked always blocks, fixes #857 | Clifford Wolf | 2019-03-07 | 1 | -15/+18 | |
| | | |/ | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | Merge pull request #848 from YosysHQ/clifford/fix763 | Clifford Wolf | 2019-03-02 | 1 | -1/+5 | |
| | | |\ | | | | | | | | | Fix error for wire decl in always block, fixes 763 | |||||
| | | | * | Fix error for wire decl in always block, fixes #763 | Clifford Wolf | 2019-03-02 | 1 | -1/+5 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | Only run derive on blackbox modules when ports have dynamic size | Clifford Wolf | 2019-03-02 | 2 | -0/+20 | |
| | | |/ | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | Fix $global_clock handling vs autowire | Clifford Wolf | 2019-03-02 | 1 | -1/+1 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | Fix $readmem[hb] for mem2reg memories, fixes #785 | Clifford Wolf | 2019-03-02 | 1 | -0/+35 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | Use mem2reg on memories that only have constant-index write ports | Clifford Wolf | 2019-03-01 | 2 | -0/+13 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | Improve "read" error msg | Clifford Wolf | 2019-02-28 | 1 | -1/+1 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Add author name | Eddie Hung | 2019-03-19 | 1 | -0/+1 | |
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| * | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-02-26 | 3 | -12/+23 | |
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| | * | | Fix handling of defparam for when default_nettype is none | Clifford Wolf | 2019-02-24 | 1 | -0/+4 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Check if Verific was built with DB_PRESERVE_INITIAL_VALUE | Clifford Wolf | 2019-02-24 | 1 | -0/+4 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Fixes related to handling of autowires and upto-ranges, fixes #814 | Clifford Wolf | 2019-02-21 | 2 | -9/+12 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Fix handling of expression width in $past, fixes #810 | Clifford Wolf | 2019-02-21 | 1 | -1/+1 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Fix segfault in printing of some internal error messages | Clifford Wolf | 2019-02-21 | 1 | -2/+2 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | parse_xaiger() to really pass single and multi-bit inout tests | Eddie Hung | 2019-02-26 | 1 | -10/+12 | |
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| * | | | parse_xaiger() to cope with multi bit inouts | Eddie Hung | 2019-02-26 | 1 | -0/+11 | |
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| * | | | parse_xaiger() to untransform $inout.out output ports | Eddie Hung | 2019-02-25 | 1 | -5/+20 | |
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| * | | | read_aiger to accept empty string for clk_name, passable only if no latches | Eddie Hung | 2019-02-25 | 1 | -0/+2 | |
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| * | | | read_aiger to work with symbol table | Eddie Hung | 2019-02-21 | 1 | -8/+47 | |
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| * | | | Add attribution | Eddie Hung | 2019-02-21 | 1 | -1/+1 | |
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| * | | | Merge branch 'read_aiger' into xaig | Eddie Hung | 2019-02-21 | 1 | -2/+7 | |
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| | * | | Fix for using POSIX basename | Eddie Hung | 2019-02-19 | 1 | -2/+4 | |
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| | * | | Missing OSX headers? | Eddie Hung | 2019-02-17 | 1 | -0/+5 | |
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| | * | | read_aiger to ignore line after ands for ascii, not binary | Eddie Hung | 2019-02-17 | 1 | -2/+1 | |
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| | * | | Merge https://github.com/YosysHQ/yosys into read_aiger | Eddie Hung | 2019-02-17 | 1 | -5/+4 | |
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| * | | | read_aiger to not do -purge for clean | Eddie Hung | 2019-02-20 | 1 | -1/+1 | |
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| * | | | lut/not/and suffix to be ${lut,not,and} | Eddie Hung | 2019-02-20 | 1 | -13/+13 | |
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| * | | | read_aiger to also rename 0 index lut when wideports | Eddie Hung | 2019-02-20 | 1 | -2/+14 | |
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| * | | | read_aiger: new naming fixes | Eddie Hung | 2019-02-20 | 1 | -5/+5 | |
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| * | | | read_aiger to name wires with internal name, less likely to clash | Eddie Hung | 2019-02-20 | 1 | -18/+15 | |
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index : iCE40/yosys | |
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