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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-26 12:04:45 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-26 12:04:45 -0800 |
| commit | da076344cc4a1777a4c4220b71aefd3768dcfd0b (patch) | |
| tree | 30a73dc20482cd73562dd1e6f8781c322e1d3753 /frontends | |
| parent | 3ea0161ae7f6111cb435c839eff694476a6527ab (diff) | |
| download | yosys-da076344cc4a1777a4c4220b71aefd3768dcfd0b.tar.gz yosys-da076344cc4a1777a4c4220b71aefd3768dcfd0b.tar.bz2 yosys-da076344cc4a1777a4c4220b71aefd3768dcfd0b.zip | |
parse_xaiger() to really pass single and multi-bit inout tests
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 9a9f2b2d8..c882f8512 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -380,20 +380,22 @@ void AigerReader::parse_xaiger() else if (c == 'o') wire = outputs[l1]; else log_abort(); - if (wideports && (wire->port_input || wire->port_output)) { - RTLIL::IdString escaped_symbol; + RTLIL::IdString escaped_s = RTLIL::escape_id(s); + + if (escaped_s.ends_with("$inout.out")) { + deferred_inouts.emplace_back(wire, escaped_s.substr(0, escaped_s.size()-10)); + goto next_line; + } + else if (wideports && (wire->port_input || wire->port_output)) { + RTLIL::IdString wide_symbol; int index; - std::tie(escaped_symbol,index) = wideports_split(RTLIL::escape_id(s)); - if (escaped_symbol.size() > 10 && escaped_symbol.substr(escaped_symbol.size()-10) == "$inout.out") { - deferred_inouts.emplace_back(wire, stringf("%s[%d]", escaped_symbol.substr(0, escaped_symbol.size()-10).c_str(), index)); + std::tie(wide_symbol,index) = wideports_split(escaped_s.str()); + if (wide_symbol.ends_with("$inout.out")) { + deferred_inouts.emplace_back(wire, stringf("%s[%d]", wide_symbol.substr(0, wide_symbol.size()-10).c_str(), index)); goto next_line; } } - - if (s.size() > 10 && s.substr(s.size()-10) == "$inout.out") - deferred_inouts.emplace_back(wire, RTLIL::escape_id(s.substr(0, s.size()-10))); - else - deferred_renames.emplace_back(wire, RTLIL::escape_id(s)); + deferred_renames.emplace_back(wire, escaped_s); next_line: std::getline(f, line); // Ignore up to start of next line |