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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-25 15:34:02 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-25 15:34:02 -0800 |
| commit | 721f6a14fb632b671ba10ed13cafad1263e2b073 (patch) | |
| tree | 71c940fbf95a5f15be3489043a42dfe3424cf287 /frontends | |
| parent | 0ca3fd6a1cca6f12db4069ed6f73b814aee2eeaf (diff) | |
| download | yosys-721f6a14fb632b671ba10ed13cafad1263e2b073.tar.gz yosys-721f6a14fb632b671ba10ed13cafad1263e2b073.tar.bz2 yosys-721f6a14fb632b671ba10ed13cafad1263e2b073.zip | |
read_aiger to accept empty string for clk_name, passable only if no latches
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index c8ba1bffd..a64729a27 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -524,6 +524,7 @@ void AigerReader::parse_aiger_ascii() // Parse latches RTLIL::Wire *clk_wire = nullptr; if (L > 0) { + log_assert(clk_name != ""); clk_wire = module->wire(clk_name); log_assert(!clk_wire); log_debug("Creating %s\n", clk_name.c_str()); @@ -654,6 +655,7 @@ void AigerReader::parse_aiger_binary() // Parse latches RTLIL::Wire *clk_wire = nullptr; if (L > 0) { + log_assert(clk_name != ""); clk_wire = module->wire(clk_name); log_assert(!clk_wire); log_debug("Creating %s\n", clk_name.c_str()); |