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* Fix variable name typo in verificsva.ccClifford Wolf2018-03-101-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for trivial SVA sequences and propertiesClifford Wolf2018-03-101-12/+102
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Use Verific hier_tree component for elaborationClifford Wolf2018-03-081-0/+54
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix Verific handling of "assert property (..);" in always blockClifford Wolf2018-03-073-14/+60
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "verific -import -V"Clifford Wolf2018-03-072-6/+18
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Set Verific db_preserve_user_nets flagClifford Wolf2018-03-071-0/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Update comment about supported SVA in verificsva.ccClifford Wolf2018-03-061-51/+8
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add SVA NON_CONSECUTIVE_REPEAT and GOTO_REPEAT supportClifford Wolf2018-03-061-20/+41
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add SVA first_match() supportClifford Wolf2018-03-061-0/+16
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add SVA within supportClifford Wolf2018-03-061-2/+18
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for SVA sequence intersectClifford Wolf2018-03-061-36/+251
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add get_fsm_accept_reject for parsing SVA propertiesClifford Wolf2018-03-061-73/+86
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Simplified SVA "until" handlingClifford Wolf2018-03-061-25/+16
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add proper SVA seq.triggered supportClifford Wolf2018-03-043-37/+102
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add Verific SVA support for "seq and seq" expressionsClifford Wolf2018-03-041-24/+94
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Refactor Verific SVA importer property parserClifford Wolf2018-03-041-56/+82
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add VerificClocking class and refactor Verific DFF handlingClifford Wolf2018-03-043-126/+196
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add SVA support for sequence ORClifford Wolf2018-03-031-22/+33
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of SVA "until seq.triggered" propertiesClifford Wolf2018-03-021-7/+25
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Update SVA cheat sheet in verificsva.ccClifford Wolf2018-03-021-2/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix in Verific SVA importer handling of until_withClifford Wolf2018-03-011-7/+5
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixes and improvements in Verific SVA importerClifford Wolf2018-03-013-83/+136
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add $rose/$fell support to Verific bindingsClifford Wolf2018-03-011-3/+22
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for PRIM_SVA_UNTIL to new SVA importerClifford Wolf2018-02-281-0/+27
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add DFSM generator to verific SVA importerClifford Wolf2018-02-281-19/+272
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Continue refactoring of Verific SVA importer codeClifford Wolf2018-02-283-671/+172
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Major redesign of Verific SVA importerClifford Wolf2018-02-271-5/+573
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add handling of verific OPER_REDUCE_NORClifford Wolf2018-02-261-0/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add handling of verific OPER_SELECTOR and OPER_WIDE_SELECTORClifford Wolf2018-02-261-0/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add handling of verific OPER_NTO1MUX and OPER_WIDE_NTO1MUXClifford Wolf2018-02-261-0/+25
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "SVA syntax cheat sheet" comment to verificsva.ccClifford Wolf2018-02-261-0/+34
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add $allconst and $allseq cell typesClifford Wolf2018-02-233-4/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add Verific SVA support for ranges in repetition operatorClifford Wolf2018-02-221-5/+26
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* Add support for SVA throughout via VerificClifford Wolf2018-02-211-2/+6
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* Add support for SVA sequence concatenation ranges via verificClifford Wolf2018-02-181-16/+124
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for SVA until statements via VerificClifford Wolf2018-02-182-34/+119
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Move Verific SVA importer to extra C++ source fileClifford Wolf2018-02-184-1279/+1370
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge Verific SVA preprocessor and SVA importerClifford Wolf2018-02-181-79/+44
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2018-02-161-0/+6
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| * Improve handling of "bus" pins in liberty front-end (some files use ↵Clifford Wolf2018-02-151-0/+6
| | | | | | | | | | | | bus.pin.direction) Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFFClifford Wolf2018-02-151-1/+1
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* Fix single-bit $stable handling in verific front-endClifford Wolf2018-02-011-0/+22
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add Verific attribute handling for assert/assume/cover/live/fair cellsClifford Wolf2018-01-311-10/+16
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix permissions on verific vdb filesClifford Wolf2018-01-281-0/+1
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* Fixed handling of synchronous and asynchronous assertion/assumption/cover in ↵Clifford Wolf2018-01-231-27/+29
| | | | | | verific bindings Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for "yosys -E"Clifford Wolf2018-01-072-2/+5
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #479 from Fatsie/latch_without_dataClifford Wolf2018-01-051-4/+23
|\ | | | | Some standard cell libraries include a latch with only set/reset.
| * Some standard cell libraries include a latch with only set/reset.Staf Verhaegen2018-01-031-4/+23
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* | Bugfix in hierarchy handling of blackbox module portsClifford Wolf2018-01-052-2/+2
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Bugfix in verilog_defaults argument parserClifford Wolf2017-12-241-1/+1
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