iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Changed the AST genWidthRTLIL subst interface to use a std::map	Clifford Wolf	2014-08-14	3	-21/+31
*	Fixed line numbers when using here-doc macros	Clifford Wolf	2014-08-14	1	-4/+9
*	Fixed handling of task outputs	Clifford Wolf	2014-08-14	1	-2/+4
*	Added module->ports	Clifford Wolf	2014-08-14	2	-0/+2
*	Added support for non-standard """ macro bodies	Clifford Wolf	2014-08-13	1	-1/+12
*	Fixed building verific bindings	Clifford Wolf	2014-08-12	2	-3/+3
*	Also allow "module foobar(input foo, output bar, ...);" syntax	Clifford Wolf	2014-08-07	1	-3/+5
*	Added AST_MULTIRANGE (arrays with more than 1 dimension)	Clifford Wolf	2014-08-06	4	-5/+80
*	Improved scope resolution of local regs in Verilog+AST frontend	Clifford Wolf	2014-08-05	3	-9/+27
*	Fixed AST handling of variables declared inside a functions main block	Clifford Wolf	2014-08-05	1	-3/+3
*	Added support for non-standard "module mod_name(...);" syntax	Clifford Wolf	2014-08-04	1	-1/+7
*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02	2	-16/+16
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-6/+6
*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02	2	-3/+3
*	Replaced sha1 implementation	Clifford Wolf	2014-08-01	1	-27/+2
*	Fixed build of verific bindings	Clifford Wolf	2014-07-31	1	-11/+11
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	3	-85/+85
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	4	-11/+11
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	16	-47/+108
*	Fixed counting verilog line numbers for "// synopsys translate_off" sections	Clifford Wolf	2014-07-30	2	-4/+4
*	Fixed Verilog pre-processor for files with no trailing newline	Clifford Wolf	2014-07-29	1	-1/+1
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	1	-5/+11
*	Removed left over debug code	Clifford Wolf	2014-07-28	2	-2/+0
*	Fixed part selects of parameters	Clifford Wolf	2014-07-28	2	-7/+31
*	Set results of out-of-bounds static bit/part select to undef	Clifford Wolf	2014-07-28	1	-5/+31
*	Fixed RTLIL code generator for part select of parameter	Clifford Wolf	2014-07-28	1	-2/+2
*	Fixed width detection for part selects	Clifford Wolf	2014-07-28	1	-2/+2
*	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28	4	-13/+17
*	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28	3	-1/+8
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	8	-38/+32
*	Fixed signdness detection of expressions with bit- and part-selects	Clifford Wolf	2014-07-28	1	-0/+1
*	Added proper Design->addModule interface	Clifford Wolf	2014-07-27	1	-0/+1
*	Fixed verific bindings for new RTLIL api	Clifford Wolf	2014-07-27	2	-55/+42
*	Fixed ilang parser for new RTLIL API	Clifford Wolf	2014-07-27	1	-10/+10
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	2	-7/+7
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-2/+2
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	2	-8/+8
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	2	-16/+11
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	1	-1/+1
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	2	-3/+3
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	3	-88/+88
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	3	-89/+89
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	3	-113/+34
*	Fixed two memory leaks in ast simplify	Clifford Wolf	2014-07-25	1	-1/+6
*	Updated verific build/test instructions	Clifford Wolf	2014-07-25	2	-13/+11
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-7/+7
*	Added "make PRETTY=1"	Clifford Wolf	2014-07-24	2	-6/+6
*	Various fixes in Verific frontend for new RTLIL API	Clifford Wolf	2014-07-23	2	-27/+55
*	Various small fixes (from gcc compiler warnings)	Clifford Wolf	2014-07-23	1	-1/+1
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-11/+0