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author | Clifford Wolf <clifford@clifford.at> | 2014-07-28 19:38:30 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-28 19:38:30 +0200 |
commit | 48822e79a34880c5f0b07e9889e463e7b6d7111b (patch) | |
tree | 801926693e8c9e4fe25a4ed570ad386e2da09fc6 /frontends | |
parent | ec589659674ba9699b5dc73129ad69f25738e87e (diff) | |
download | yosys-48822e79a34880c5f0b07e9889e463e7b6d7111b.tar.gz yosys-48822e79a34880c5f0b07e9889e463e7b6d7111b.tar.bz2 yosys-48822e79a34880c5f0b07e9889e463e7b6d7111b.zip |
Removed left over debug code
Diffstat (limited to 'frontends')
-rw-r--r-- | frontends/ast/genrtlil.cc | 1 | ||||
-rw-r--r-- | frontends/ast/simplify.cc | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 9b8e0faa4..cb666679b 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -917,7 +917,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) children[0]->children[1]->clone() : children[0]->children[0]->clone()); fake_ast->children[0]->delete_children(); RTLIL::SigSpec shift_val = fake_ast->children[1]->genRTLIL(); - log_dump(width, shift_val, id2ast->range_swapped, source_width, id2ast->range_left, id2ast->range_right); if (id2ast->range_right != 0) shift_val = current_module->Sub(NEW_ID, shift_val, id2ast->range_right); if (id2ast->range_swapped) diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index d47bfb5e6..5665cd43c 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1535,7 +1535,6 @@ skip_dynamic_range_lvalue_expansion:; tmp_range_left = (param_width + 2*param_offset) - children[0]->range_right - 1; tmp_range_right = (param_width + 2*param_offset) - children[0]->range_left - 1; } - log_dump(param_upto, param_offset, param_width, children[0]->range_left, children[0]->range_right, tmp_range_left, tmp_range_right); for (int i = tmp_range_right; i <= tmp_range_left; i++) { int index = i - param_offset; if (0 <= index && index < param_width) |