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* Add -noautowire option to verilog frontendMarcus Comstedt2015-08-011-1/+8
* Added WORDS parameter to $meminitClifford Wolf2015-07-313-7/+67
* Fixed nested mem2regClifford Wolf2015-07-292-4/+11
* Fixed trailing whitespacesClifford Wolf2015-07-0220-49/+49
* Fixed handling of parameters with reversed rangeClifford Wolf2015-06-081-1/+1
* Fixed signedness of genvar expressionsClifford Wolf2015-05-291-2/+2
* Improvements in BLIF front-endClifford Wolf2015-05-241-4/+50
* bugfix in blif front-endClifford Wolf2015-05-181-3/+3
* Improved .latch support in BLIF front-endClifford Wolf2015-05-171-3/+30
* Added read_blif commandClifford Wolf2015-05-171-1/+31
* Generalized blifparse APIClifford Wolf2015-05-172-17/+25
* abc/blifparse files reorganizationClifford Wolf2015-05-173-0/+298
* Verific build fixesClifford Wolf2015-05-172-2/+2
* Verilog front-end: define `BLACKBOX in -lib modeClifford Wolf2015-04-191-1/+2
* Ignore celldefine directive in verilog front-endClifford Wolf2015-03-251-0/+3
* Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()Clifford Wolf2015-03-011-2/+4
* Added non-std verilog assume() statementClifford Wolf2015-02-268-13/+37
* Added deep recursion warning to AST simplifyClifford Wolf2015-02-201-1/+7
* Parser support for complex delay expressionsClifford Wolf2015-02-202-8/+21
* YosysJS stuffClifford Wolf2015-02-191-0/+1
* Convert floating point cell parameters to stringsClifford Wolf2015-02-181-9/+12
* Various fixes for memories with offsetsClifford Wolf2015-02-142-6/+5
* Added "read_verilog -nomeminit" and "nomeminit" attributeClifford Wolf2015-02-144-7/+29
* Creating $meminit cells in verilog front-endClifford Wolf2015-02-144-33/+57
* Fixed handling of "//" in filenames in verilog pre-processorClifford Wolf2015-02-142-1/+5
* Added AstNode::simplify() recursion counterClifford Wolf2015-02-131-2/+10
* Improved read_verilog support for empty behavioral statementsClifford Wolf2015-02-101-6/+2
* Ignore explicit assignments to constants in HDL codeClifford Wolf2015-02-081-0/+14
* Fixed a bug with autowire bit sizeClifford Wolf2015-02-081-9/+3
* Added ENABLE_NDEBUG makefile optionsClifford Wolf2015-01-241-0/+2
* Ignoring more system task and functionsClifford Wolf2015-01-152-2/+4
* Fixed handling of "input foo; reg [0:0] foo;"Clifford Wolf2015-01-151-0/+7
* Consolidate "Blocking assignment to memory.." msgs for the same lineClifford Wolf2015-01-151-3/+9
* Enable bison to be customizedFabio Utzig2015-01-082-2/+2
* Define YOSYS and SYNTHESIS in preprocClifford Wolf2015-01-021-1/+2
* Fixed memory->start_offset handlingClifford Wolf2015-01-012-6/+10
* Added global yosys_celltypesClifford Wolf2014-12-291-1/+1
* dict/pool changes in astClifford Wolf2014-12-293-16/+24
* Changed more code to dict<> and pool<>Clifford Wolf2014-12-283-6/+6
* Improved some warning messagesClifford Wolf2014-12-271-6/+18
* Fixed mem2reg warning messageClifford Wolf2014-12-271-3/+3
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-263-3/+3
* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-241-1/+1
* Fixed supply0/supply1 with many wiresClifford Wolf2014-12-111-3/+15
* Fixed minor bug in parsing delaysClifford Wolf2014-11-241-1/+4
* Fixed two minor bugs in constant parsingClifford Wolf2014-11-242-3/+7
* Added warning for use of 'z' constants in HDLClifford Wolf2014-11-143-6/+14
* Fixed parsing of nested verilog concatenation and replicateClifford Wolf2014-11-121-1/+1
* Added log_warning() APIClifford Wolf2014-11-094-17/+17
* Added "ENABLE_PLUGINS := 0" to verific amd64 build instructionsClifford Wolf2014-11-081-0/+1
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