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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-15 12:53:12 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-15 12:53:12 +0100 |
| commit | a588a4a5c95d14e62678c98b14af139903980be3 (patch) | |
| tree | 10a0ec49e5e637f73077e81f9d7b0e602e85374f /frontends | |
| parent | 8e8e791fb5dba3eb0a236cbed8c13bd5ac5ce96c (diff) | |
| download | yosys-a588a4a5c95d14e62678c98b14af139903980be3.tar.gz yosys-a588a4a5c95d14e62678c98b14af139903980be3.tar.bz2 yosys-a588a4a5c95d14e62678c98b14af139903980be3.zip | |
Fixed handling of "input foo; reg [0:0] foo;"
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/simplify.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 5ab778e66..552fc04bc 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -186,6 +186,13 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, AstNode *first_node = this_wire_scope[node->str]; if (!node->is_input && !node->is_output && node->is_reg && node->children.size() == 0) goto wires_are_compatible; + if (first_node->children.size() == 0 && node->children.size() == 1 && node->children[0]->type == AST_RANGE) { + AstNode *r = node->children[0]; + if (r->range_valid && r->range_left == 0 && r->range_right == 0) { + delete r; + node->children.pop_back(); + } + } if (first_node->children.size() != node->children.size()) goto wires_are_incompatible; for (size_t j = 0; j < node->children.size(); j++) { |