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Author
Age
Files
Lines
*
Improve Verific SVA importer
Clifford Wolf
2017-07-27
1
-0
/
+34
*
Add log_warning_noprefix() API, Use for Verific warnings and errors
Clifford Wolf
2017-07-27
1
-1
/
+1
*
Add "verific -import -n" and "verific -import -nosva"
Clifford Wolf
2017-07-27
1
-14
/
+36
*
Improve Verific SVA import: negedge and $past
Clifford Wolf
2017-07-27
1
-6
/
+49
*
Improve Verific SVA importer
Clifford Wolf
2017-07-27
1
-37
/
+58
*
Improve Verific bindings (mostly related to SVA)
Clifford Wolf
2017-07-26
1
-110
/
+320
*
Improve "help verific" message
Clifford Wolf
2017-07-25
1
-5
/
+5
*
Add "verific -extnets"
Clifford Wolf
2017-07-25
1
-23
/
+130
*
Improve "verific -all" handling
Clifford Wolf
2017-07-25
1
-26
/
+45
*
Add "verific -import -d <dump_file"
Clifford Wolf
2017-07-24
1
-6
/
+35
*
Add "verific -import -flatten" and "verific -import -v"
Clifford Wolf
2017-07-24
1
-107
/
+164
*
Add "verific -import -k"
Clifford Wolf
2017-07-22
1
-42
/
+51
*
Improve docs for verific bindings, add simply sby example
Clifford Wolf
2017-07-22
5
-48
/
+89
*
Fix "read_blif -wideports" handling of cells with wide ports
Clifford Wolf
2017-07-21
1
-3
/
+33
*
Add a paragraph about pre-defined macros to read_verilog help message
Clifford Wolf
2017-07-21
1
-0
/
+4
*
Add attributes and parameter support to JSON front-end
Clifford Wolf
2017-07-10
1
-7
/
+50
*
Add JSON front-end
Clifford Wolf
2017-07-08
2
-0
/
+472
*
Add Verific Release information to log
Clifford Wolf
2017-07-04
1
-0
/
+12
*
Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand cons...
Clifford Wolf
2017-06-07
2
-0
/
+8
*
Fix handling of Verilog ~& and ~| operators
Clifford Wolf
2017-06-01
1
-0
/
+8
*
Add support for localparam in module header
Clifford Wolf
2017-04-30
1
-1
/
+7
*
Add support for `resetall compiler directive
Clifford Wolf
2017-04-26
1
-0
/
+7
*
Fix verilog pre-processor for multi-level relative includes
Clifford Wolf
2017-03-14
1
-4
/
+26
*
Allow $anyconst, etc. in non-formal SV mode
Clifford Wolf
2017-03-01
1
-1
/
+1
*
Add $live and $fair cell types, add support for s_eventually keyword
Clifford Wolf
2017-02-25
6
-4
/
+40
*
Add support for SystemVerilog unique, unique0, and priority case
Clifford Wolf
2017-02-23
2
-4
/
+25
*
Preserve string parameters
Clifford Wolf
2017-02-23
1
-2
/
+8
*
Added SystemVerilog support for ++ and --
Clifford Wolf
2017-02-23
2
-1
/
+12
*
Fix incorrect "incompatible re-declaration of wire" error in tasks/functions
Clifford Wolf
2017-02-14
1
-2
/
+9
*
Add support for verific mem initialization
Clifford Wolf
2017-02-11
1
-0
/
+38
*
Fix another stupid bug in the same line
Clifford Wolf
2017-02-11
1
-1
/
+1
*
Add verific support for initialized variables
Clifford Wolf
2017-02-11
1
-3
/
+47
*
Improve handling of Verific warnings and error messages
Clifford Wolf
2017-02-11
1
-4
/
+10
*
Fix extremely stupid typo
Clifford Wolf
2017-02-11
1
-1
/
+1
*
Add checker support to verilog front-end
Clifford Wolf
2017-02-09
2
-11
/
+24
*
Add "rand" and "rand const" verific support
Clifford Wolf
2017-02-09
1
-0
/
+41
*
Add SV "rand" and "const rand" support
Clifford Wolf
2017-02-08
2
-8
/
+28
*
Add PSL parser mode to verific front-end
Clifford Wolf
2017-02-08
1
-2
/
+17
*
Add "read_blif -wideports"
Clifford Wolf
2017-02-06
2
-5
/
+77
*
Further improve cover() support
Clifford Wolf
2017-02-04
1
-0
/
+6
*
Add $cover cell type and SVA cover() support
Clifford Wolf
2017-02-04
7
-5
/
+16
*
Add assert/assume support to verific front-end
Clifford Wolf
2017-02-04
2
-625
/
+687
*
Add "enum" and "typedef" lexer support
Clifford Wolf
2017-01-17
2
-1
/
+4
*
Fix bug in AstNode::mem2reg_as_needed_pass2()
Clifford Wolf
2017-01-15
1
-0
/
+2
*
Fixed handling of local memories in functions
Clifford Wolf
2017-01-05
1
-2
/
+2
*
Added handling of local memories and error for local decls in unnamed blocks
Clifford Wolf
2017-01-04
1
-1
/
+10
*
Added Verilog $rtoi and $itor support
Clifford Wolf
2017-01-03
1
-24
/
+30
*
Added "verilog_defines" command
Clifford Wolf
2016-12-15
1
-0
/
+60
*
Added support for macros as include file names
Clifford Wolf
2016-11-28
1
-0
/
+2
*
Bugfix in "read_verilog -D NAME=VAL" handling
Clifford Wolf
2016-11-28
1
-3
/
+3
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