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* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-062-5/+9
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| * | Merge pull request #1551 from whitequark/manual-cell-operandsClifford Wolf2019-12-051-5/+5
| |\ \ | | | | | | | | Clarify semantics of comb cells, in particular shifts
| | * | kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.whitequark2019-12-041-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, these cells would accept any \B_SIGNED and in case of \B_SIGNED=1, would still treat the \B input as unsigned. Also fix the Verilog frontend to never emit such constructs.
| * | | read_ilang: do bounds checking on bit indicesMarcin Kościelnicki2019-11-271-0/+4
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* | | Call abc9 with "&write -n", and parse_xaiger() to copeEddie Hung2019-12-061-92/+85
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* | | Do not connect undriven POs to 1'bxEddie Hung2019-12-061-8/+3
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* | | Merge branch 'eddie/clkpart' into xaig_dffEddie Hung2019-11-225-18/+88
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| * | Add Verific support for SVA nexttime propertiesClifford Wolf2019-11-221-0/+22
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improve handling of verific primitives in "verific -import -V" modeClifford Wolf2019-11-221-2/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add Verific SVA support for "always" propertiesClifford Wolf2019-11-221-5/+15
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | sv: Correct parsing of always_comb, always_ff and always_latchDavid Shah2019-11-212-5/+40
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | Correctly treat empty modules as blackboxes in VerificClifford Wolf2019-11-201-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Do not rename VHDL entities to "entity(impl)" when they are top modulesClifford Wolf2019-11-202-5/+8
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Consistent log message, ignore 's' extensionEddie Hung2019-11-201-2/+3
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-199-33/+260
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| * Add check for valid macro names in macro definitionsClifford Wolf2019-11-071-7/+11
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Improve naming scheme for (VHDL) modules imported from VerificClifford Wolf2019-10-241-3/+26
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add "verific -L"Clifford Wolf2019-10-241-1/+12
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add "verilog_defines -list" and "verilog_defines -reset"Clifford Wolf2019-10-211-0/+16
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Fix handling of "restrict" in Verific front-endClifford Wolf2019-10-211-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Fix parsing of .cname BLIF statementsClifford Wolf2019-10-161-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add .blackbox support to blif front-endClifford Wolf2019-10-161-0/+6
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Use "(id)" instead of "id" for types as temporary hackClifford Wolf2019-10-145-20/+187
| |\ | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * frontends/ast: code styleDavid Shah2019-10-031-2/+1
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * sv: Fix typedefs in blocksDavid Shah2019-10-031-2/+2
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * sv: Disambiguate interface portsDavid Shah2019-10-031-3/+19
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * sv: Fix memories of typedefsDavid Shah2019-10-031-1/+1
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * sv: Add %expectDavid Shah2019-10-031-0/+1
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * sv: Add support for memories of a typedefDavid Shah2019-10-031-6/+20
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * sv: Add support for memory typedefsDavid Shah2019-10-032-3/+34
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * sv: Fix typedefs in packagesDavid Shah2019-10-031-4/+10
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * sv: Fix typedef parametersDavid Shah2019-10-032-6/+48
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * sv: Switch parser to glr, prep for typedefDavid Shah2019-10-035-11/+89
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-081-2/+6
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| * | Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9Eddie Hung2019-10-081-4/+4
| |\ \ | | | | | | | | Rename abc_* names/attributes to more precisely be abc9_*
| * | | Fixes for MSVC buildMiodrag Milanovic2019-10-041-2/+6
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* | | | Fix merge issuesEddie Hung2019-10-041-1/+1
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* | | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dffEddie Hung2019-10-041-4/+4
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| * | | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-4/+4
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* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-033-35/+61
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| * | Merge pull request #1419 from YosysHQ/eddie/lazy_deriveClifford Wolf2019-10-032-35/+59
| |\ \ | | |/ | |/| module->derive() to be lazy and not touch ast if already derived
| | * Fix for svinterfacesEddie Hung2019-09-301-2/+8
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| | * module->derive() to be lazy and not touch ast if already derivedEddie Hung2019-09-302-33/+51
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| * | Define environ, fixes #1424Miodrag Milanovic2019-10-011-0/+2
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* | Cleanup $currQ from aigerparseEddie Hung2019-09-301-2/+0
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-303-2/+597
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| * Merge pull request #1406 from whitequark/connect_rpcwhitequark2019-09-302-0/+591
| |\ | | | | | | rpc: new frontend
| | * rpc: new frontend.whitequark2019-09-302-0/+591
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A new pass, connect_rpc, allows any HDL frontend that can read/write JSON from/to stdin/stdout or an unix socket or a named pipe to participate in elaboration as a first class citizen, such that any other HDL supported by Yosys directly or indirectly can transparently instantiate modules handled by this frontend. Recognizing that many HDL frontends emit Verilog, it allows the RPC frontend to direct Yosys to process the result of instantiation via any built-in Yosys frontend. The resulting RTLIL is then hygienically integrated into the overall design.
| * | Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_inMiodrag Milanović2019-09-301-2/+6
| |\ \ | | | | | | | | Open aig frontend as binary file
| | * | Fix reading aig files on windowsMiodrag Milanovic2019-09-291-1/+5
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