iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Fixed temp net name generation in rtlil process generator for abbreviated ↵	Clifford Wolf	2013-11-28	1	-0/+2
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*	Added "src" attribute to processes	Clifford Wolf	2013-11-28	1	-0/+1
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*	Added module->avail_parameters (for advanced techmap features)	Clifford Wolf	2013-11-24	1	-1/+5
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*	Added verilog frontend -ignore_redef option	Clifford Wolf	2013-11-24	3	-5/+19
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*	Early wire/reg/parameter width calculation in ast/simplify	Clifford Wolf	2013-11-24	1	-0/+5
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*	Added support for signed parameters in ilang	Clifford Wolf	2013-11-24	2	-1/+8
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*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24	5	-56/+4
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*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24	3	-3/+7
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*	Improved handling of initialized registers	Clifford Wolf	2013-11-23	1	-10/+10
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*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22	2	-2/+2
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*	Fixed O(n^2) performance bug in verilog preprocessor	Clifford Wolf	2013-11-22	1	-1/+1
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*	Enable {* .. *} feature per default (removes dependency to REJECT feature in ↵	Clifford Wolf	2013-11-22	4	-22/+2
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*	Fixed async proc detection in mem2reg	Clifford Wolf	2013-11-21	1	-5/+9
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*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21	5	-88/+255
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*	Fixed ilang parser: memory width	Clifford Wolf	2013-11-20	1	-1/+1
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*	Another name resolution bugfix for generate blocks	Clifford Wolf	2013-11-20	1	-4/+13
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*	Implemented indexed part selects	Clifford Wolf	2013-11-20	2	-0/+14
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*	Do not allow memory bit select on the left side of an assignment	Clifford Wolf	2013-11-20	1	-1/+1
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*	Added "synthesis" in (synopsys\|synthesis) comment support	Clifford Wolf	2013-11-20	1	-6/+6
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*	Fixed name resolution of local tasks and functions in generate block	Clifford Wolf	2013-11-20	1	-2/+16
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*	Implemented part/bit select on memory read	Clifford Wolf	2013-11-20	2	-4/+63
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*	Added init= attribute for fpga-style reset values	Clifford Wolf	2013-11-20	1	-6/+19
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*	Fixed parsing of module arguments when one type is used for many args	Clifford Wolf	2013-11-19	1	-3/+10
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*	Fixed two bugs in mem2reg functionality in AST frontend	Clifford Wolf	2013-11-18	1	-4/+8
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*	Added dumping of attributes in AST frontend	Clifford Wolf	2013-11-18	1	-0/+11
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*	Fixed parsing of default cases when not last case	Clifford Wolf	2013-11-18	1	-12/+16
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*	Fixed mem2reg for reg usage outside always block	Clifford Wolf	2013-11-18	1	-1/+1
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*	Fixed parsing of "parameter integer"	Clifford Wolf	2013-11-13	1	-2/+2
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*	Cleanups and bugfixes in response to new internal cell checker	Clifford Wolf	2013-11-11	1	-3/+6
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*	Call internal checker more often	Clifford Wolf	2013-11-10	1	-0/+1
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*	More undef-propagation related fixes	Clifford Wolf	2013-11-08	1	-0/+4
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*	Fixed handling of different signedness in power operands	Clifford Wolf	2013-11-08	1	-1/+1
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*	Implemented const folding of ternary op with undef select	Clifford Wolf	2013-11-08	1	-0/+8
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*	Fixed handling of power operator	Clifford Wolf	2013-11-07	2	-10/+22
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*	Fixed more extend vs. extend_u0 issues	Clifford Wolf	2013-11-07	2	-3/+3
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*	Disabled const folding of ternary op when select is undef	Clifford Wolf	2013-11-07	1	-2/+14
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*	Renamed extend_un0() to extend_u0() and use it in genrtlil	Clifford Wolf	2013-11-07	1	-4/+8
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*	Fixed sign handling in constants	Clifford Wolf	2013-11-07	1	-0/+1
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*	Fixed const folding in corner cases with parameters	Clifford Wolf	2013-11-07	2	-14/+27
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*	Fixed width detection for replicate operator	Clifford Wolf	2013-11-07	1	-0/+1
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*	Fixed at_zero evaluation of dynamic ranges	Clifford Wolf	2013-11-07	1	-7/+2
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*	Various fixes for correct parameter support	Clifford Wolf	2013-11-07	4	-40/+101
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*	Fixed the fix for propagation of width hints for $signed() and $unsigned()	Clifford Wolf	2013-11-07	1	-5/+4
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*	Fixed propagation of width hints for $signed() and $unsigned()	Clifford Wolf	2013-11-06	1	-1/+4
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*	Additional fixes for undef propagation in concat and replicate ops	Clifford Wolf	2013-11-06	1	-0/+4
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*	Improved width extension with regard to undef propagation	Clifford Wolf	2013-11-06	1	-9/+60
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*	Another fix for early width and sign detection in ast simplifier	Clifford Wolf	2013-11-04	1	-2/+3
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*	Fixed const folding of ternary operator	Clifford Wolf	2013-11-04	1	-4/+5
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*	Use proper bit width ans sign extension for const folding	Clifford Wolf	2013-11-04	1	-17/+18
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*	Fixes for early width and sign detection in ast simplifier	Clifford Wolf	2013-11-04	1	-1/+2
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