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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-08 11:40:36 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-08 11:40:36 +0100 |
| commit | 259cc1391e1e53455d9919af453b78198454e13a (patch) | |
| tree | 6dd4a5c39c4f075228e145b3c5adeb152f724a84 /frontends | |
| parent | 9f49d538e1e6bd59c848f19226c95949ba2f37b5 (diff) | |
| download | yosys-259cc1391e1e53455d9919af453b78198454e13a.tar.gz yosys-259cc1391e1e53455d9919af453b78198454e13a.tar.bz2 yosys-259cc1391e1e53455d9919af453b78198454e13a.zip | |
More undef-propagation related fixes
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 2e8ab7492..25781ae23 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1116,6 +1116,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) detectSignWidth(width_hint, sign_hint); RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint); RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint); + #if 0 int width = std::max(left.width, right.width); if (width > width_hint && width_hint > 0) width = width_hint; @@ -1127,6 +1128,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (type == AST_MUL) width = std::min(left.width + right.width, width_hint); } + #else + int width = std::max(std::max(left.width, right.width), width_hint); + #endif is_signed = children[0]->is_signed && children[1]->is_signed; return binop2rtlil(this, type_name, width, left, right); } |