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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-06 22:41:21 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-06 22:41:21 +0100 |
| commit | 7fe13faefae1e81ce68a399ae09ef396245b4c29 (patch) | |
| tree | 4800073ef4bfc210e672a0e1733ec6cabb66ed95 /frontends | |
| parent | 8c523ef81d615515a2bf56e0886c5fad1aae85ad (diff) | |
| download | yosys-7fe13faefae1e81ce68a399ae09ef396245b4c29.tar.gz yosys-7fe13faefae1e81ce68a399ae09ef396245b4c29.tar.bz2 yosys-7fe13faefae1e81ce68a399ae09ef396245b4c29.zip | |
Fixed propagation of width hints for $signed() and $unsigned()
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index f3ca0c787..ce34f708a 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -950,7 +950,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // just pass thru the signal. the parent will evaluated the is_signed property and inperpret the SigSpec accordingly case AST_TO_SIGNED: case AST_TO_UNSIGNED: { - RTLIL::SigSpec sig = children[0]->genRTLIL(); + int sub_width_hint; + bool sub_sign_hint; + children[0]->detectSignWidth(sub_width_hint, sub_sign_hint); + RTLIL::SigSpec sig = children[0]->genRTLIL(width_hint, sub_sign_hint); is_signed = sign_hint; return sig; } |