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Age
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Fix input/output attributes when resolving typedef of wire
Kamil Rakoczy
2021-01-18
1
-0
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+3
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Parse package user type in module port list
Lukasz Dalek
2021-01-18
1
-30
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+32
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Merge pull request #2518 from zachjs/recursion
whitequark
2021-01-01
2
-8
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+28
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verilog: improved support for recursive functions
Zachary Snow
2020-12-31
2
-8
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+28
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sv: complete support for implied task/function port directions
Zachary Snow
2020-12-31
1
-0
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+10
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Fix elaboration of whole memory words used as indices
Zachary Snow
2020-12-26
1
-1
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+8
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Fix constants bound to redeclared function args
Zachary Snow
2020-12-26
1
-5
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+16
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Merge pull request #2501 from zachjs/genrtlil-tern-sign
whitequark
2020-12-23
1
-0
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+1
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genrtlil: fix mux2rtlil generated wire signedness
Zachary Snow
2020-12-22
1
-0
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+1
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Merge pull request #2476 from zachjs/const-arg-width
whitequark
2020-12-23
1
-0
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+8
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Fix constants bound to single bit arguments (fixes #2383)
Zachary Snow
2020-12-22
1
-0
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+8
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Merge pull request #2479 from zachjs/const-arg-hint
whitequark
2020-12-22
1
-0
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+5
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Allow constant function calls in constant function arguments
Zachary Snow
2020-12-07
1
-0
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+5
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Sign extend port connections where necessary
Zachary Snow
2020-12-18
1
-2
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+24
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Merge pull request #2456 from Zottel/master
whitequark
2020-12-02
1
-0
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+1
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Return correct modname when found in cache.
Julius Roob
2020-11-26
1
-0
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+1
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Bump required Verific version
Miodrag Milanovic
2020-12-02
1
-1
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+1
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Fix SYNTHESIS always being defined in Verilog frontend
georgerennie
2020-12-01
2
-1
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+3
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rtlil: remove dotted identifiers.
whitequark
2020-11-25
1
-1
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+0
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Update verific version
Miodrag Milanovic
2020-10-30
1
-1
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+1
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Fix argument handling in connect_rpc
Claire Xenia Wolf
2020-10-19
1
-1
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+2
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extend verific library API for formal apps and generators
Miodrag Milanovic
2020-10-12
1
-15
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+83
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Update required Verific version
Miodrag Milanović
2020-10-05
1
-1
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+1
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Ignore empty parameters in Verilog module instantiations
Claire Xenia Wolf
2020-10-01
1
-0
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+3
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Merge pull request #2378 from udif/pr_dollar_high_low
clairexen
2020-10-01
3
-31
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+98
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We can now handle array slices (e.g. $size(x[1]) etc. )
Udi Finkelstein
2020-09-17
1
-7
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+6
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Fixed comments, removed debug message
Udi Finkelstein
2020-09-16
1
-5
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+5
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Added $high(), $low(), $left(), $right()
Udi Finkelstein
2020-09-15
3
-30
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+98
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use sha1 for parameter list in case if they contain spaces
Miodrag Milanovic
2020-09-30
1
-2
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+18
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Better error for unsupported SVA sequence
Miodrag Milanovic
2020-09-18
1
-2
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+8
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Merge pull request #2329 from antmicro/arrays-fix-multirange-size
clairexen
2020-09-17
1
-2
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+11
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Rewrite multirange arrays sizes [n] as [n-1:0]
Lukasz Dalek
2020-08-03
1
-2
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+11
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Merge pull request #2330 from antmicro/arrays-fix-multirange-access
clairexen
2020-09-17
1
-1
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+1
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Fix subarray access condition
Lukasz Dalek
2020-08-03
1
-1
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+1
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Use latest verific
Miodrag Milanovic
2020-09-02
1
-1
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+1
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Merge pull request #2352 from zachjs/const-func-localparam
clairexen
2020-09-01
1
-0
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+12
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Allow localparams in constant functions
Zachary Snow
2020-08-20
1
-0
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+12
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Merge pull request #2366 from zachjs/library-format
clairexen
2020-09-01
1
-0
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+11
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Simple support for %l format specifier
Zachary Snow
2020-08-29
1
-0
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+11
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Merge pull request #2353 from zachjs/top-scope
clairexen
2020-09-01
1
-0
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+7
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Module name scope support
Zachary Snow
2020-08-20
1
-0
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+7
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Merge pull request #2365 from zachjs/const-arg-loop-split-type
clairexen
2020-09-01
1
-3
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+4
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Fix constant args used with function ports split across declarations
Zachary Snow
2020-08-29
1
-3
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+4
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Reorder to prevent crash
Miodrag Milanovic
2020-08-31
1
-3
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+3
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ast recognize lower case x and z and verific gives upper case
Miodrag Milanovic
2020-08-30
1
-2
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+6
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Do not check for 1 and 0 only
Miodrag Milanovic
2020-08-30
1
-6
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+0
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Fix import of VHDL enums
Miodrag Milanovic
2020-08-30
1
-11
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+22
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Replace "ILANG" with "RTLIL" everywhere.
whitequark
2020-08-26
9
-91
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+106
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Add formal apps and template generators
Miodrag Milanovic
2020-08-26
1
-1
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+223
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Merge pull request #2122 from PeterCrozier/struct_array2
clairexen
2020-08-19
1
-28
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+62
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