iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixed build of verific bindings	Clifford Wolf	2014-07-31	1	-11/+11
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	3	-85/+85
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	4	-11/+11
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	16	-47/+108
*	Fixed counting verilog line numbers for "// synopsys translate_off" sections	Clifford Wolf	2014-07-30	2	-4/+4
*	Fixed Verilog pre-processor for files with no trailing newline	Clifford Wolf	2014-07-29	1	-1/+1
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	1	-5/+11
*	Removed left over debug code	Clifford Wolf	2014-07-28	2	-2/+0
*	Fixed part selects of parameters	Clifford Wolf	2014-07-28	2	-7/+31
*	Set results of out-of-bounds static bit/part select to undef	Clifford Wolf	2014-07-28	1	-5/+31
*	Fixed RTLIL code generator for part select of parameter	Clifford Wolf	2014-07-28	1	-2/+2
*	Fixed width detection for part selects	Clifford Wolf	2014-07-28	1	-2/+2
*	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28	4	-13/+17
*	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28	3	-1/+8
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	8	-38/+32
*	Fixed signdness detection of expressions with bit- and part-selects	Clifford Wolf	2014-07-28	1	-0/+1
*	Added proper Design->addModule interface	Clifford Wolf	2014-07-27	1	-0/+1
*	Fixed verific bindings for new RTLIL api	Clifford Wolf	2014-07-27	2	-55/+42
*	Fixed ilang parser for new RTLIL API	Clifford Wolf	2014-07-27	1	-10/+10
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	2	-7/+7
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-2/+2
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	2	-8/+8
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	2	-16/+11
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	1	-1/+1
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	2	-3/+3
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	3	-88/+88
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	3	-89/+89
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	3	-113/+34
*	Fixed two memory leaks in ast simplify	Clifford Wolf	2014-07-25	1	-1/+6
*	Updated verific build/test instructions	Clifford Wolf	2014-07-25	2	-13/+11
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-7/+7
*	Added "make PRETTY=1"	Clifford Wolf	2014-07-24	2	-6/+6
*	Various fixes in Verific frontend for new RTLIL API	Clifford Wolf	2014-07-23	2	-27/+55
*	Various small fixes (from gcc compiler warnings)	Clifford Wolf	2014-07-23	1	-1/+1
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-11/+0
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-2/+2
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-2/+2
*	SigSpec refactoring: More cleanups of old SigSpec use pattern	Clifford Wolf	2014-07-22	1	-3/+6
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22	1	-1/+1
*	SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only	Clifford Wolf	2014-07-22	2	-92/+17
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	3	-82/+82
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	3	-82/+82
*	Fixed ilang parsing of process attributes	Clifford Wolf	2014-07-22	1	-0/+1
*	Fixed make rules for ilang parser	Clifford Wolf	2014-07-22	1	-1/+3
*	Added "autoidx" statement to ilang file format	Clifford Wolf	2014-07-21	2	-25/+10
*	Replaced depricated NEW_WIRE macro with module->addWire() calls	Clifford Wolf	2014-07-21	1	-10/+10
*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21	1	-5/+5
*	Implemented dynamic bit-/part-select for memory writes	Clifford Wolf	2014-07-17	1	-2/+26
*	Added support for bit/part select to mem2reg rewriter	Clifford Wolf	2014-07-17	1	-0/+9
*	Added support for constant bit- or part-select for memory writes	Clifford Wolf	2014-07-17	1	-9/+36