iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Be more conservative with new const-function code	Clifford Wolf	2014-02-14	1	-1/+5
*	Added support for FOR loops in function calls in parameters	Clifford Wolf	2014-02-14	3	-0/+43
*	Created basic support for function calls in parameter values	Clifford Wolf	2014-02-14	4	-49/+184
*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13	3	-59/+90
*	Added support for functions returning integer	Clifford Wolf	2014-02-12	1	-2/+12
*	renamed ilang "scope error" to "ilang error"	Clifford Wolf	2014-02-11	1	-9/+9
*	Improved ilang parser error messages	Clifford Wolf	2014-02-09	1	-9/+9
*	Fixed gcc compiler warnings with release build	Clifford Wolf	2014-02-06	1	-1/+1
*	Added read_verilog -setattr	Clifford Wolf	2014-02-05	1	-0/+15
*	Fixed bug in sequential sat proofs and improved handling of asserts	Clifford Wolf	2014-02-04	1	-0/+2
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	1	-0/+1
*	Added support for blanks after -I and -D in read_verilog	Clifford Wolf	2014-02-02	1	-7/+20
*	Fixed comment/eol parsing in ilang frontend	Clifford Wolf	2014-02-01	2	-22/+25
*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01	5	-0/+44
*	Bugfix in name resolution with generate blocks	Clifford Wolf	2014-01-30	1	-1/+1
*	Added read_verilog -icells option	Clifford Wolf	2014-01-29	4	-6/+20
*	Fixed handling of unsized constants in verilog frontend	Clifford Wolf	2014-01-24	1	-2/+2
*	Fixed algorithmic complexity of AST simplification of long expressions	Clifford Wolf	2014-01-20	3	-6/+13
*	Added $assert cell	Clifford Wolf	2014-01-19	2	-0/+92
*	Added Verilog parser support for asserts	Clifford Wolf	2014-01-19	4	-3/+12
*	Fixed parsing of verilog macros at end of line	Clifford Wolf	2014-01-18	1	-1/+1
*	Added verilog_defaults command	Clifford Wolf	2014-01-17	1	-0/+66
*	Fixed typo in frontends/ast/simplify.cc	Clifford Wolf	2014-01-12	1	-1/+1
*	Added updating of RTLIL::autoidx to ilang frontend	Clifford Wolf	2014-01-03	1	-1/+23
*	Added correct handling of $memwr priority	Clifford Wolf	2014-01-03	1	-0/+2
*	Fixed a stupid access after delete bug	Clifford Wolf	2013-12-29	1	-1/+2
*	Fixed parsing of non-arg macro calls followed by "("	Clifford Wolf	2013-12-27	1	-1/+7
*	Fixed parsing of macros with no arguments and expansion text starting with "("	Clifford Wolf	2013-12-27	1	-1/+2
*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27	1	-2/+2
*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27	6	-15/+37
*	Added elsif preproc support	Clifford Wolf	2013-12-18	1	-1/+14
*	Added support for macro arguments	Clifford Wolf	2013-12-18	1	-23/+75
*	Keep strings as strings in const ternary and concat	Clifford Wolf	2013-12-05	3	-5/+25
*	Added const folding support for $signed and $unsigned	Clifford Wolf	2013-12-05	1	-0/+7
*	Added AstNode::mkconst_str API	Clifford Wolf	2013-12-05	3	-12/+19
*	Fixed generate-for (and disabled double warning for auto-wire)	Clifford Wolf	2013-12-04	1	-1/+5
*	Added support for $clog2 system function	Clifford Wolf	2013-12-04	1	-4/+20
*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04	6	-7/+134
*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04	4	-8/+4
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	3	-24/+37
*	Added support for local regs in named blocks	Clifford Wolf	2013-12-04	3	-2/+30
*	Fixed temp net name generation in rtlil process generator for abbreviated nam...	Clifford Wolf	2013-11-28	1	-0/+2
*	Added "src" attribute to processes	Clifford Wolf	2013-11-28	1	-0/+1
*	Added module->avail_parameters (for advanced techmap features)	Clifford Wolf	2013-11-24	1	-1/+5
*	Added verilog frontend -ignore_redef option	Clifford Wolf	2013-11-24	3	-5/+19
*	Early wire/reg/parameter width calculation in ast/simplify	Clifford Wolf	2013-11-24	1	-0/+5
*	Added support for signed parameters in ilang	Clifford Wolf	2013-11-24	2	-1/+8
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24	5	-56/+4
*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24	3	-3/+7
*	Improved handling of initialized registers	Clifford Wolf	2013-11-23	1	-10/+10