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* Add missing "[options]" to read_blif helpEddie Hung2019-02-081-1/+1
* Allow module name to be determined by argument tooEddie Hung2019-02-082-14/+44
* Refactor into AigerReader classEddie Hung2019-02-082-79/+92
* Parse binary AIG filesEddie Hung2019-02-081-49/+164
* Refactor to parse_aiger_header()Eddie Hung2019-02-081-26/+32
* Add commentEddie Hung2019-02-081-0/+1
* Handle reset logic in latchesEddie Hung2019-02-081-2/+17
* Change literal vars from int to unsignedEddie Hung2019-02-081-1/+1
* Create clk outside of latch loopEddie Hung2019-02-081-7/+9
* Handle latch symbols tooEddie Hung2019-02-081-3/+1
* Remove return after log_errorEddie Hung2019-02-081-27/+9
* Add support for symbol tablesEddie Hung2019-02-081-1/+49
* Stub for binary AIGEREddie Hung2019-02-081-3/+8
* RefactorEddie Hung2019-02-061-1/+8
* WIPEddie Hung2019-02-063-0/+247
* Bugfix in Verilog string handlingClifford Wolf2019-01-051-1/+1
* Remove -m32 Verific eval lib build instructionsClifford Wolf2019-01-041-29/+0
* Improve VerificImporter support for writes to asymmetric memoriesClifford Wolf2019-01-021-22/+35
* Fix VerificImporter asymmetric memories error messageClifford Wolf2019-01-021-1/+1
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-025-11/+11
* Add "read_ilang -[no]overwrite"Clifford Wolf2018-12-233-4/+54
* Fix segfault in AST simplifyClifford Wolf2018-12-181-0/+5
* Improve src tagging (using names and attrs) of cells and wires in verific fro...Clifford Wolf2018-12-182-99/+160
* read_ilang: allow slicing sigspecs.whitequark2018-12-161-10/+6
* verilog_parser: Properly handle recursion when processing attributesSylvain Munaut2018-12-141-19/+29
* Verific updatesClifford Wolf2018-12-061-53/+0
* Make return value of $clog2 signedSylvain Munaut2018-11-241-1/+1
* Set Verific flag vhdl_support_variable_slice=1Clifford Wolf2018-11-091-0/+1
* Allow square brackets in liberty identifiersClifford Wolf2018-11-051-1/+2
* Add warning for SV "restrict" without "property"Clifford Wolf2018-11-041-2/+11
* Various indenting fixes in AST front-end (mostly space vs tab issues)Clifford Wolf2018-11-043-99/+69
* Make and dependent upon LSB onlyZipCPU2018-11-031-2/+8
* Do not generate "reg assigned in a continuous assignment" warnings for "rand ...Clifford Wolf2018-11-011-2/+15
* Fix minor typo in error messageClifford Wolf2018-10-251-1/+1
* Merge pull request #679 from udif/pr_syntax_errorClifford Wolf2018-10-251-14/+14
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| * Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars...Udi Finkelstein2018-10-251-14/+14
* | Improve read_verilog range out of bounds warningClifford Wolf2018-10-201-6/+6
* | Refactor code to avoid code duplication + added commentsRuben Undheim2018-10-203-134/+108
* | Support for SystemVerilog interfaces as a port in the top level module + test...Ruben Undheim2018-10-201-3/+105
* | Fixed memory leakRuben Undheim2018-10-201-0/+1
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* Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-186-14/+353
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| * Handle FIXME for modport members without type directly in frontRuben Undheim2018-10-131-6/+8
| * Documentation improvements etc.Ruben Undheim2018-10-132-8/+35
| * Fix build error with clangRuben Undheim2018-10-121-1/+1
| * Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-124-8/+89
| * Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-126-14/+243
* | Merge pull request #664 from tklam/ignore-verilog-protectClifford Wolf2018-10-181-0/+3
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| * | ignore protect endprotectargama2018-10-161-0/+3
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* | Minor code cleanups in liberty front-endClifford Wolf2018-10-171-16/+5
* | Merge pull request #660 from tklam/parse-liberty-detect-ff-latchClifford Wolf2018-10-171-0/+17
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