| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Ignore celldefine directive in verilog front-end | Clifford Wolf | 2015-03-25 | 1 | -0/+3 |
| * | Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker() | Clifford Wolf | 2015-03-01 | 1 | -2/+4 |
| * | Added non-std verilog assume() statement | Clifford Wolf | 2015-02-26 | 8 | -13/+37 |
| * | Added deep recursion warning to AST simplify | Clifford Wolf | 2015-02-20 | 1 | -1/+7 |
| * | Parser support for complex delay expressions | Clifford Wolf | 2015-02-20 | 2 | -8/+21 |
| * | YosysJS stuff | Clifford Wolf | 2015-02-19 | 1 | -0/+1 |
| * | Convert floating point cell parameters to strings | Clifford Wolf | 2015-02-18 | 1 | -9/+12 |
| * | Various fixes for memories with offsets | Clifford Wolf | 2015-02-14 | 2 | -6/+5 |
| * | Added "read_verilog -nomeminit" and "nomeminit" attribute | Clifford Wolf | 2015-02-14 | 4 | -7/+29 |
| * | Creating $meminit cells in verilog front-end | Clifford Wolf | 2015-02-14 | 4 | -33/+57 |
| * | Fixed handling of "//" in filenames in verilog pre-processor | Clifford Wolf | 2015-02-14 | 2 | -1/+5 |
| * | Added AstNode::simplify() recursion counter | Clifford Wolf | 2015-02-13 | 1 | -2/+10 |
| * | Improved read_verilog support for empty behavioral statements | Clifford Wolf | 2015-02-10 | 1 | -6/+2 |
| * | Ignore explicit assignments to constants in HDL code | Clifford Wolf | 2015-02-08 | 1 | -0/+14 |
| * | Fixed a bug with autowire bit size | Clifford Wolf | 2015-02-08 | 1 | -9/+3 |
| * | Added ENABLE_NDEBUG makefile options | Clifford Wolf | 2015-01-24 | 1 | -0/+2 |
| * | Ignoring more system task and functions | Clifford Wolf | 2015-01-15 | 2 | -2/+4 |
| * | Fixed handling of "input foo; reg [0:0] foo;" | Clifford Wolf | 2015-01-15 | 1 | -0/+7 |
| * | Consolidate "Blocking assignment to memory.." msgs for the same line | Clifford Wolf | 2015-01-15 | 1 | -3/+9 |
| * | Enable bison to be customized | Fabio Utzig | 2015-01-08 | 2 | -2/+2 |
| * | Define YOSYS and SYNTHESIS in preproc | Clifford Wolf | 2015-01-02 | 1 | -1/+2 |
| * | Fixed memory->start_offset handling | Clifford Wolf | 2015-01-01 | 2 | -6/+10 |
| * | Added global yosys_celltypes | Clifford Wolf | 2014-12-29 | 1 | -1/+1 |
| * | dict/pool changes in ast | Clifford Wolf | 2014-12-29 | 3 | -16/+24 |
| * | Changed more code to dict<> and pool<> | Clifford Wolf | 2014-12-28 | 3 | -6/+6 |
| * | Improved some warning messages | Clifford Wolf | 2014-12-27 | 1 | -6/+18 |
| * | Fixed mem2reg warning message | Clifford Wolf | 2014-12-27 | 1 | -3/+3 |
| * | Added Yosys::{dict,nodict,vector} container types | Clifford Wolf | 2014-12-26 | 3 | -3/+3 |
| * | Renamed extend() to extend_xx(), changed most users to extend_u0() | Clifford Wolf | 2014-12-24 | 1 | -1/+1 |
| * | Fixed supply0/supply1 with many wires | Clifford Wolf | 2014-12-11 | 1 | -3/+15 |
| * | Fixed minor bug in parsing delays | Clifford Wolf | 2014-11-24 | 1 | -1/+4 |
| * | Fixed two minor bugs in constant parsing | Clifford Wolf | 2014-11-24 | 2 | -3/+7 |
| * | Added warning for use of 'z' constants in HDL | Clifford Wolf | 2014-11-14 | 3 | -6/+14 |
| * | Fixed parsing of nested verilog concatenation and replicate | Clifford Wolf | 2014-11-12 | 1 | -1/+1 |
| * | Added log_warning() API | Clifford Wolf | 2014-11-09 | 4 | -17/+17 |
| * | Added "ENABLE_PLUGINS := 0" to verific amd64 build instructions | Clifford Wolf | 2014-11-08 | 1 | -0/+1 |
| * | Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..." | Clifford Wolf | 2014-10-30 | 1 | -4/+5 |
| * | AST simplifier: optimize constant AST_CASE nodes before recursively descending | Clifford Wolf | 2014-10-29 | 1 | -31/+35 |
| * | Added support for task and function args in parentheses | Clifford Wolf | 2014-10-27 | 1 | -6/+45 |
| * | Improvements in $readmem[bh] implementation | Clifford Wolf | 2014-10-26 | 1 | -8/+13 |
| * | Added support for $readmemh/$readmemb | Clifford Wolf | 2014-10-26 | 2 | -0/+113 |
| * | Fixed constant "cond ? string1 : string2" with strings of different size | Clifford Wolf | 2014-10-25 | 1 | -0/+2 |
| * | Re-introduced Yosys::readsome() helper function | Clifford Wolf | 2014-10-23 | 3 | -15/+5 |
| * | minor indenting corrections | Clifford Wolf | 2014-10-19 | 1 | -2/+2 |
| * | Builds on Mac 10.9.2 with LLVM 3.5. | Parviz Palangpour | 2014-10-19 | 1 | -0/+5 |
| * | Fixed various VS warnings | Clifford Wolf | 2014-10-18 | 1 | -1/+1 |
| * | Header changes so it will compile on VS | William Speirs | 2014-10-17 | 2 | -4/+10 |
| * | Wrapped math in int constructor | William Speirs | 2014-10-17 | 1 | -1/+1 |
| * | Print "SystemVerilog" in "read_verilog -sv" log messages | Clifford Wolf | 2014-10-16 | 1 | -1/+1 |
| * | Fixed handling of invalid array access in mem2reg code | Clifford Wolf | 2014-10-16 | 2 | -3/+15 |
