aboutsummaryrefslogtreecommitdiffstats
path: root/frontends
Commit message (Expand)AuthorAgeFilesLines
* Fix segfault in AST simplifyClifford Wolf2018-12-181-0/+5
* Improve src tagging (using names and attrs) of cells and wires in verific fro...Clifford Wolf2018-12-182-99/+160
* read_ilang: allow slicing sigspecs.whitequark2018-12-161-10/+6
* verilog_parser: Properly handle recursion when processing attributesSylvain Munaut2018-12-141-19/+29
* Verific updatesClifford Wolf2018-12-061-53/+0
* Make return value of $clog2 signedSylvain Munaut2018-11-241-1/+1
* Set Verific flag vhdl_support_variable_slice=1Clifford Wolf2018-11-091-0/+1
* Allow square brackets in liberty identifiersClifford Wolf2018-11-051-1/+2
* Add warning for SV "restrict" without "property"Clifford Wolf2018-11-041-2/+11
* Various indenting fixes in AST front-end (mostly space vs tab issues)Clifford Wolf2018-11-043-99/+69
* Make and dependent upon LSB onlyZipCPU2018-11-031-2/+8
* Do not generate "reg assigned in a continuous assignment" warnings for "rand ...Clifford Wolf2018-11-011-2/+15
* Fix minor typo in error messageClifford Wolf2018-10-251-1/+1
* Merge pull request #679 from udif/pr_syntax_errorClifford Wolf2018-10-251-14/+14
|\
| * Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars...Udi Finkelstein2018-10-251-14/+14
* | Improve read_verilog range out of bounds warningClifford Wolf2018-10-201-6/+6
* | Refactor code to avoid code duplication + added commentsRuben Undheim2018-10-203-134/+108
* | Support for SystemVerilog interfaces as a port in the top level module + test...Ruben Undheim2018-10-201-3/+105
* | Fixed memory leakRuben Undheim2018-10-201-0/+1
|/
* Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-186-14/+353
|\
| * Handle FIXME for modport members without type directly in frontRuben Undheim2018-10-131-6/+8
| * Documentation improvements etc.Ruben Undheim2018-10-132-8/+35
| * Fix build error with clangRuben Undheim2018-10-121-1/+1
| * Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-124-8/+89
| * Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-126-14/+243
* | Merge pull request #664 from tklam/ignore-verilog-protectClifford Wolf2018-10-181-0/+3
|\ \
| * | ignore protect endprotectargama2018-10-161-0/+3
| |/
* | Minor code cleanups in liberty front-endClifford Wolf2018-10-171-16/+5
* | Merge pull request #660 from tklam/parse-liberty-detect-ff-latchClifford Wolf2018-10-171-0/+17
|\ \
| * | detect ff/latch before processing other nodesargama2018-10-141-0/+17
| |/
* | Merge pull request #638 from udif/pr_reg_wire_errorClifford Wolf2018-10-171-0/+12
|\ \ | |/ |/|
| * Fixed issue #630 by fixing a minor typo in the previous commitUdi Finkelstein2018-09-251-2/+2
| * Merge branch 'master' into pr_reg_wire_errorUdi Finkelstein2018-09-1821-479/+1448
| |\
| * | Fixed remaining cases where we check fo wire reg/wire incorrect assignmentsUdi Finkelstein2018-09-181-0/+12
* | | Improve Verific importer blackbox handlingClifford Wolf2018-10-071-2/+14
* | | Fix compiler warning in verific.ccClifford Wolf2018-10-051-0/+2
* | | Fix for issue 594.Tom Verbeure2018-10-021-1/+2
* | | Add read_verilog $changed supportDan Gisselquist2018-10-011-1/+4
* | | Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosysClifford Wolf2018-09-301-1/+1
|\ \ \
| * | | Fix handling of $past 2nd argument in read_verilogClifford Wolf2018-09-301-1/+1
| | |/ | |/|
* | | Add "read_verilog -noassert -noassume -assert-assumes"Clifford Wolf2018-09-243-6/+49
* | | Added support for ommited "parameter" in Verilog-2001 style parameter decl in...Clifford Wolf2018-09-231-3/+9
|/ /
* | Add "verific -L <int>" optionClifford Wolf2018-09-043-2/+16
* | Add "make coverage"Clifford Wolf2018-08-276-12/+10
* | Merge pull request #610 from udif/udif_specify_round2Clifford Wolf2018-08-231-16/+39
|\ \
| * | Fixed all known specify/endspecify issues, without breaking 'make test'.Udi Finkelstein2018-08-201-12/+12
| * | Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-rout...Udi Finkelstein2018-08-201-10/+22
| * | A few minor enhancements to specify block parsing.Udi Finkelstein2018-08-151-2/+13
* | | Added -no_dump_ptr flag for AST dump options in 'read_verilog'Udi Finkelstein2018-08-233-9/+20
* | | Add "verific -work" help messageClifford Wolf2018-08-221-0/+7
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-22 14:35:07 +0000