iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fix handling of cases that look like sva labels, fixes #862	Clifford Wolf	2019-03-10	2	-92/+66
*	Merge pull request #858 from YosysHQ/clifford/svalabels	Clifford Wolf	2019-03-09	5	-56/+201
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\| *	Also add support for labels on sva module items, fixes #699	Clifford Wolf	2019-03-08	2	-44/+113
\| *	Add support for SVA labels in read_verilog	Clifford Wolf	2019-03-07	3	-26/+89
\| *	Add hack for handling SVA labels via Verific	Clifford Wolf	2019-03-07	1	-1/+14
* \|	Update help message for -chparam	Eddie Hung	2019-03-09	1	-1/+2
* \|	Add -chparam option to verific command	Eddie Hung	2019-03-09	1	-2/+18
* \|	Fix spelling	Eddie Hung	2019-03-09	1	-1/+1
* \|	Fix handling of task output ports in clocked always blocks, fixes #857	Clifford Wolf	2019-03-07	1	-15/+18
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*	Merge pull request #848 from YosysHQ/clifford/fix763	Clifford Wolf	2019-03-02	1	-1/+5
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\| *	Fix error for wire decl in always block, fixes #763	Clifford Wolf	2019-03-02	1	-1/+5
* \|	Only run derive on blackbox modules when ports have dynamic size	Clifford Wolf	2019-03-02	2	-0/+20
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*	Fix $global_clock handling vs autowire	Clifford Wolf	2019-03-02	1	-1/+1
*	Fix $readmem[hb] for mem2reg memories, fixes #785	Clifford Wolf	2019-03-02	1	-0/+35
*	Use mem2reg on memories that only have constant-index write ports	Clifford Wolf	2019-03-01	2	-0/+13
*	Improve "read" error msg	Clifford Wolf	2019-02-28	1	-1/+1
*	Fix handling of defparam for when default_nettype is none	Clifford Wolf	2019-02-24	1	-0/+4
*	Check if Verific was built with DB_PRESERVE_INITIAL_VALUE	Clifford Wolf	2019-02-24	1	-0/+4
*	Fixes related to handling of autowires and upto-ranges, fixes #814	Clifford Wolf	2019-02-21	2	-9/+12
*	Fix handling of expression width in $past, fixes #810	Clifford Wolf	2019-02-21	1	-1/+1
*	Fix segfault in printing of some internal error messages	Clifford Wolf	2019-02-21	1	-2/+2
*	Fix sign handling of real constants	Clifford Wolf	2019-02-13	1	-5/+4
*	Bugfix in Verilog string handling	Clifford Wolf	2019-01-05	1	-1/+1
*	Remove -m32 Verific eval lib build instructions	Clifford Wolf	2019-01-04	1	-29/+0
*	Improve VerificImporter support for writes to asymmetric memories	Clifford Wolf	2019-01-02	1	-22/+35
*	Fix VerificImporter asymmetric memories error message	Clifford Wolf	2019-01-02	1	-1/+1
*	Fix typographical and grammatical errors and inconsistencies.	whitequark	2019-01-02	5	-11/+11
*	Add "read_ilang -[no]overwrite"	Clifford Wolf	2018-12-23	3	-4/+54
*	Fix segfault in AST simplify	Clifford Wolf	2018-12-18	1	-0/+5
*	Improve src tagging (using names and attrs) of cells and wires in verific fro...	Clifford Wolf	2018-12-18	2	-99/+160
*	read_ilang: allow slicing sigspecs.	whitequark	2018-12-16	1	-10/+6
*	verilog_parser: Properly handle recursion when processing attributes	Sylvain Munaut	2018-12-14	1	-19/+29
*	Verific updates	Clifford Wolf	2018-12-06	1	-53/+0
*	Make return value of $clog2 signed	Sylvain Munaut	2018-11-24	1	-1/+1
*	Set Verific flag vhdl_support_variable_slice=1	Clifford Wolf	2018-11-09	1	-0/+1
*	Allow square brackets in liberty identifiers	Clifford Wolf	2018-11-05	1	-1/+2
*	Add warning for SV "restrict" without "property"	Clifford Wolf	2018-11-04	1	-2/+11
*	Various indenting fixes in AST front-end (mostly space vs tab issues)	Clifford Wolf	2018-11-04	3	-99/+69
*	Make and dependent upon LSB only	ZipCPU	2018-11-03	1	-2/+8
*	Do not generate "reg assigned in a continuous assignment" warnings for "rand ...	Clifford Wolf	2018-11-01	1	-2/+15
*	Fix minor typo in error message	Clifford Wolf	2018-10-25	1	-1/+1
*	Merge pull request #679 from udif/pr_syntax_error	Clifford Wolf	2018-10-25	1	-14/+14
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\| *	Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars...	Udi Finkelstein	2018-10-25	1	-14/+14
* \|	Improve read_verilog range out of bounds warning	Clifford Wolf	2018-10-20	1	-6/+6
* \|	Refactor code to avoid code duplication + added comments	Ruben Undheim	2018-10-20	3	-134/+108
* \|	Support for SystemVerilog interfaces as a port in the top level module + test...	Ruben Undheim	2018-10-20	1	-3/+105
* \|	Fixed memory leak	Ruben Undheim	2018-10-20	1	-0/+1
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*	Merge pull request #659 from rubund/sv_interfaces	Clifford Wolf	2018-10-18	6	-14/+353
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\| *	Handle FIXME for modport members without type directly in front	Ruben Undheim	2018-10-13	1	-6/+8
\| *	Documentation improvements etc.	Ruben Undheim	2018-10-13	2	-8/+35